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CHEST 2020 Research Project Abstracts

P11_20: Secure Processor Design by RISC-V Framework
Topic Areas: Design
Principal investigator: Dr. Yunsi Fei, Northeastern University
Co-Principal investigator(s): Prof. David Kaeli, Northeastern University
PI Email

The recent discovered exploits, Meltdown and Spectre, have exposed the fundamental pitfall of modern computer architecture – numerous performance features and microarchitectures have become security vulnerabilities, especially for information exfiltration across logic boundaries, e.g., user vs. kernel space boundary, host vs. enclave boundaries, etc. This project adopts the secure-by-design principle and proposes to design secure and high-performance open processor architecture based on the RISC-V framework. Associated with the processor design, we will also develop a microarchitecture software simulator and provide proof of security for our design.