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CHEST 2020 Research Project Abstracts


P4_20: Asynchronous Design for Side-Channel Avoidance
Topic Areas: Additive Manufacturing, Aging and Reliability Monitoring
Principal investigator: Rashmi Jha, University of Cincinnati
Co-Principal investigator(s): Dr. Marc Cahay, University of Cincinnati
Co-Principal investigator(s): Dr. Punit Boolchand, University of Cincinnati
PI Email

Abstract:
Continuous monitoring of Integrated Circuit (IC) aging, reliability, failure, and integrity is becoming highly important as chip design and manufacturing become more and more complex. The currently available chip odometers are based on CMOS Ring Oscillators (RO) that are not scalable and can be easily tampered and reverse-engineered. This proposal aims to explore the fundamental device physics of emerging Resistive Random Access Memory (RRAM) devices and develop their applications in IC aging, reliability, failure, and integrity monitoring. The RRAM-based monitors can be integrated additively on any pre-fabricated CMOS dies on front or back side in a trusted-foundry, thus, providing flexibility to the system designers to optimize size, weight, power, and trust of a chip on-demand basis. Additionally, integration of RRAM-based monitors in trusted foundry makes it immune to tampering which is critical for reliable monitoring of ICs. RRAM devices also offer inherent self-encryption of the aging data stored as the state change of the devices which makes this technology resistant towards tampering, reverse engineering, and side-channel attacks. The RRAM-based monitors can operate at ultra-low power and provide excellent spatial and temporal coverage of the entire ICs for its lifetime which is critical for practical integration of IC monitors.

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