P7_20: CAD Flow Development for Design Obfuscation through Post-Fabrication Transistor-Level Programming (TRAP)
Topic Areas: IP Protection
Principal investigator: Dr. Yiorgos Makris, University of Texas at Dallas
Co-Principal investigator(s): Dr. Benjamin Carrion Schaefer, University of Texas at Dallas
Co-Principal investigator(s): Dr. William Swartz Jr., University of Texas at Dallas
Protecting Intellectual Property (IP) of electronic designs from unauthorized and/or untrusted parties involved in the semiconductor manufacturing supply chain has become a topic of intense interest. Among the possible options explored to date, design obfuscation has emerged as a front-runner candidate for yielding a viable solution. To this end, we have developed a Transistor-Level Programming (TRAP) method and the corresponding post-manufacturing programmable fabric to support the design of hybrid ASIC/TRAP integrated circuits (ICs). In these ICs, sensitive or proprietary parts of the design can be obfuscated by omitting them from the blueprints submitted for fabrication and reinstating them via TRAP when the ICs are received from the foundry. In this project, we seek support to address several CAD challenges that arise in the design, manufacturing and programming of such hybrid ASIC/TRAP ICs.