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CHEST 2020 Research Project Abstracts

P8_20: Design Obfuscation and Performance Locking Solutions for Analog/RF ICs
Topic Areas: Security and Trust Solutions for Analog/Mixed-Signal/RF Circuits and Systems
Principal investigator: Dr. Yiorgos Makris, University of Texas at Dallas
Co-Principal investigator(s): Dr. Andrew Marshall, University of Texas at Dallas
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This effort seeks to develop design obfuscation and performance locking solutions for analog/RF Integrated Circuits (ICs). Unlike their digital counterparts, for which a plethora of logic locking and design obfuscation solutions have been developed in the past, the analog/RF domain has not yet received the same level of attention, mainly because the problem is fundamentally different in this domain. Indeed, digital design obfuscation relies on the sheer number of logic gates and the discrete nature of Boolean functions. Analog/RF designs, however, consist of a fairly small number of transistors interconnected in a fairly small number of known topologies for each type of component. Therefore, obfuscating the functionality of an analog/RF design is, most likely, an ineffective proposition. Instead, efforts should focus on hiding the performance of an analog/RF IC, by obfuscating the parameters of a design, as this is the true intellectual property (IP) which the designers spend the vast majority of their time on. To this end, we propose to investigate a variety of solutions for protecting the IP of an analog/RF design, by obfuscating the actual design parameters and by locking the ability to calibrate a fabricated IC within its intended specifications. The methods that will be developed in this effort will be demonstrated through Spice-level simulations on a set of example analog/RF IC designs and will be evaluated based both on the overhead they incur and on the level of protection that they achieve. While this is a challenging problem which requires longer-term research, we believe that a one-year effort will enable us to develop a convincing proof-of-concept solution which will justify subsequent investment, including demonstration of cost-effective analog/RF design obfuscation and performance locking in silicon.