P13_21: CAD Flow Development for Design Obfuscation through Post-Fabrication Transistor-Level Programming (TRAP)
Topic Areas: IP Protection
Principal investigator: Dr. Yiorgos Makris, University of Texas at Dallas
Co-Principal investigator(s): Dr. Carl Sechen and Dr. Benjamin Carrion Schaefer, University of Texas at Dallas
PI Email
Abstract:
Protecting Intellectual Property (IP) of electronic designs from unauthorized and/or untrusted parties involved in the semiconductor manufacturing supply chain has become a topic of intense interest. Among the possible options explored to date, design obfuscation has emerged as a front-runner candidate for yielding a viable solution. To this end, we have developed a Transistor-Level Programming (TRAP) method and the corresponding post-manufacturing programmable fabric to support the design of hybrid ASIC/TRAP integrated circuits (ICs). In these ICs, sensitive or proprietary parts of the design can be obfuscated by omitting them from the blueprints submitted for fabrication and reinstating them via TRAP when the ICs are received from the foundry. This multi-year project focuses on addressing the CAD challenges that arise in the design, manufacturing and programming of such hybrid ASIC/TRAP ICs. In the first year of the project, we (i) developed a high-level synthesis approach (HLS) for determining the part of a design that should be mapped to TRAP, and (ii) enabled accurate timing analysis across the entire hybrid ASIC/TRAP design. In the second year of the project, we seek support to (i) continue development of our HLS-based design space exploration, and (ii) develop a design verification methodology that leverages commercial EDA tools to prove correctness of the hybrid ASIC/TRAP design.