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CHEST 2021 Research Project Abstracts

P17_21: Secure RISC-V Processor Design, Implementation, and Simulation
Topic Areas: Design
Principal investigator: Dr. Yunsi Fei, Northeastern University
Co-Principal investigator: Dr. David Kaeli, Northeastern University
PI Email

The recent discovered exploits, Meltdown and Spectre, have exposed the fundamental pitfall of modern computer architecture – numerous performance features and microarchitectures have become security vulnerabilities, especially for information exfiltration across logic boundaries, e.g., user vs. kernel space, host vs. enclave execution environments, etc. This project adopts the secure-by-design principle and proposes to design secure and high-performance open processor architecture based on the RISC-V framework. Associated with the processor design, we are developing a RISC-V-based microarchitecture simulator named Yori, designed to unify performance and security design exploration into one cohesive process. We will provide proof of security for our design, validated by both simulation and implementation.