P20_21: NATE: A Neural Network Assisted Timing Profiler for Hardware Trojan Detection
Topic Areas: Hardware Trojan
Principal investigator: Dr. Houman Homayoun, University of California Davis
The fabless semiconductor model has left exposed critical entry points for nefarious foundries to insert hardware Trojan (HT) devices into a manufacturer’s intellectual property. Hardware Trojans range from passive “spying” devices to those which deploy catastrophic payloads to damage or maliciously operate the device. The detection of such devices is a rapidly developing area of research in hardware security. However, many of these approaches rely on side-channel power data which is becoming increasingly difficult to interpret as process nodes shrink. This proposal outlines a sophisticated approach to detecting HTs which leverages a collection of integrated circuit (IC) process reliability data extracted at the physical design level as well as a neural network (NN) implementation to leverage these reliability metrics to predict the path delays of a given IC design. This data is then analyzed to determine the presence of a hardware Trojan more accurately. In the first thrust of this research, an automated Trojan insertion software solution was developed. This innovation allows for numerous HT-infected benchmarks to be generated and used as valuable test sets for the trained NN. Additionally, an example AES cypher benchmark was taken through the ASIC flow, reliability metrics and path delays were extracted and an array of HTs were inserted into the design. In the final thrust to this work, an array of NN models will be explored to predict acceptable path delay shifts across a range of reliability parameters. Finally, several benchmarks will be explored as case studies in which the NN is trained across many different reliability corners and the resulting delay shift model will be used to accurately classify the presence of a hardware Trojan.