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CHEST 2022 Research Project Abstracts

P13_22: Scalable Security Verification Framework for Digital and Analog/Mixed-Signal System-on-Chips
Topic Areas: New Approaches to Secure On-Shore Microelectronics Design and Manufacturing
Principal investigator: Dr. Kanad Basu, University of Texas at Dallas
Co-Principal investigator(s): Dr. Yiorgos Makris, University of Texas at Dallas
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System-on-Chip (SoC) is the brain behind modern computing devices, which are being extensively used in recording, analyzing, and communicating some of our most intimate personal information including health, location, activity, etc. Reusable hardware IP-based SoC design has emerged as a pervasive design practice in the industry to dramatically reduce design and verification cost while meeting aggressive time-to-market constraints. Growing reliance on these pre-verified hardware IPs, often gathered from untrusted third-party vendors (3PIPs), severely affects the security and trustworthiness of SoC computing platforms. Based on Common Vulnerability Exposure (CVE-MITRE) estimates, if hardware-level vulnerabilities are removed, the overall system vulnerability will reduce by 43%. Existing research has demonstrated that commercial EDA tools fall short in executing security validation on a full-scale SoC. In this research, we address this critical issue, by proposing a semi-formal SoC security validation approach. Unlike formal techniques, our proposed approach doesn’t suffer from state space explosion. On the other hand, the proposed method is able to identify corner case scenarios (typically exploited for introducing security vulnerabilities), that usually remain undetected by traditional simulation-based methods. The proposed technique will be scaled for digital and analog SoC components, as well as extended for improving post-silicon security validation.