P15_22: Design Obfuscation and Performance Locking Solutions for Analog/RF ICs
Topic Areas: Security and Trust Solutions for Analog/Mixed-Signal/RF Circuits and Systems
Principal investigator: Dr. Yiorgos Makris, University of Texas at Dallas
Co-Principal investigator(s): Dr. Ken O, Dr. Andrew Marshall, University of Texas at Dallas
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Abstract:
This multi-year effort seeks to develop design obfuscation and performance locking solutions for analog/RF Integrated Circuits (ICs). Unlike their digital counterparts, for which a plethora of logic locking and design obfuscation solutions have been developed in the past, the analog/RF domain has not yet received the same level of attention, mainly because the problem is fundamentally different in this domain. Indeed, digital design obfuscation relies on the sheer number of logic gates and the discrete nature of Boolean functions. Analog/RF designs, however, consist of a fairly small number of transistors interconnected in a fairly small number of known topologies for each type of component. Therefore, obfuscating the functionality of an analog/RF design is, most likely, an ineffective proposition. Instead, efforts should focus on hiding the performance of an analog/RF IC, by obfuscating the parameters of a design, as this is the true intellectual property (IP) which the designers spend the vast majority of their time on. To this end, this multi-year project seeks to investigate a variety of solutions for protecting the IP of an analog/RF design, by obfuscating the actual design parameters and by locking the ability to calibrate a fabricated IC within its intended specifications. During the first two years of the project, we have already implemented and demonstrated two analog performance calibration locking method through the use of cyclically-connected analog floating gate transistors, which we demonstrated on an Operational Transconductance Amplifier (OTA) and through a distributed parametric obfuscation which hides multiple design parameters without digital encoding. In the third year of the project, we intend to explore a combination of several ideas that have been individually examined in the past, judiciously combine them into the strongest analog performance obfuscation method known to date, and demonstrated them on state-of-the-art RF device. Additionally, through a separate initiative within the auspices of the NSF CHEST I/UCRC, we intend to fabricate a custom IC which will showcase all of the above solutions in a contemporary technology and will corroborate their cost-effectiveness in silicon.