P16_22: CAD Flow Development for Design Obfuscation through Post-Fabrication Transistor-Level Programming (TRAP)
Topic Areas: IP Protection
Principal investigator: Dr. Yiorgos Makris, University of Texas at Dallas
Co-Principal investigator(s): Dr. Carl Sechen, Dr. Benjamin Carrion Schaefer, University of Texas at Dallas
Protecting Intellectual Property (IP) of electronic designs from unauthorized and/or untrusted parties involved in semiconductor manufacturing has become a topic of intense interest. Among the options explored to date, design obfuscation has emerged as a front-runner for yielding a viable solution. To this end, we developed a Transistor-Level Programming (TRAP) method and the corresponding post-manufacturing programmable fabric to support design of hybrid ASIC/TRAP integrated circuits (ICs). In these ICs, sensitive or proprietary parts of the design can be obfuscated by omitting them from the blueprints submitted for fabrication and reinstating them via TRAP when the ICs are received from the foundry. This multi-year project focuses on addressing the CAD challenges that arise in the design, manufacturing and programming of such hybrid ASIC/TRAP ICs. In the second year of the project, we (i) developed a high-level synthesis approach (HLS) for determining the part of a design to be mapped to TRAP, and (ii) enabled design verification across the hybrid ASIC/TRAP design. In the third year, we seek support to (i) finalize development of our HLS-based design space exploration, (ii) develop an advanced routing method, and (iii) devise a formal security evaluation solution for hybrid ASIC/TRAP designs.