P19_22: Fingerprinting FPGA Circuits Using Communication Interfaces
Topic Areas: FPGA Integrity Monitoring and Risk Mitigation
Principal investigator: Dr. Houman Homayoun, University of California Davis
Co-Principal investigator(s): Dr. J. M. Emmert, University of Cincinnati
Nowadays, heterogeneous hardware has been a trend, both in cloud and edge devices. FPGAs have become widely deployed in public clouds by cloud providers such as Amazon and Microsoft Azure. Also, there are new types of heterogeneous hardware in the edge devices, e.g., SoC-FPGAs that integrate CPUs and FPGAs. However, this exposes the vulnerabilities of FPGAs to malicious attackers as well. It has been demonstrated in the literature that power side-channel attacks, fault attacks, etc. are capable of being deployed on FPGAs and can potentially compromise the security of a multi-tenant FPGA in a cloud environment. For adversaries to successfully launch these attacks, it is essential to obtain information about whether the victim exists on the targeted fabric and what type of application is being performed. This critical step is not the focus of previous studies, but finding out possible related vulnerabilities in FPGAs in a heterogeneous computing system and developing mitigations to prevent attackers from obtaining such information can significantly increase the difficulty of launching such attacks. This motivates us to explore possible vulnerabilities in FPGA communication interfaces to fingerprint customized circuits running on FPGAs and provide mitigations. This project aims to exploit information leakage in PCIe communications and other communication protocols that widely exist in FPGA heterogeneous computing systems to help fingerprint customized FPGA circuits deployed on the same FPGA board. In the first thrust, we aim to develop a benchmark that measures performance data of communication interfaces and captures the communication patterns of neighboring circuits by collecting data traces. Our target in this step is to prove that the communication side-channel in heterogeneous computing systems can be a potential weakness and attack surface. In the second thrust, we aim to develop a machine learning classifier such that the collected data traces can be processed to reveal the identity of the co-located circuits. Mitigation techniques will be developed to be used in both cloud infrastructure and edge devices.