P20_22: Translation of Learning models into Logic for Real-Time Hardware monitoring and Security
Principal investigator: Dr. Avesta Sasan, University of California Davis
Co-Principal investigator(s): Dr. Houman Homayoun, University of California Davis
In this work, we seek to build a compiler solution that translates a neural network to a memorized decision tree implemented in FPGA or ASIC while satisfying the chip designer's PPA constraints. While it is expected that aggressive PPA constraints would result in a drop in model accuracy after translation, we aim to explore various translation solutions to minimize the accuracy drop. From a mathematical standpoint, the confidence created by many lower accuracy predictions can substantially be higher than the confidence created by infrequent yet high accuracy predictions within the same time interval. Moreover, the logic-based (ASIC or FPGA) implementation of a NN is verifiable. ML solutions are considered "black box," whereas, in logic, the correct operation and the rationale for a decision could be verified, allowing us to reason for decisions made and reject or accept the decision as a means of false-positive reduction.
After developing this flow, we plan to use the memorized ML solutions for building a wide range of ML-assisted hardware security solutions, including 1) Behavior classification models for anomaly detection; 2) Real-time attack detection (malware, trojan, Ransomware, power attack, cache-based attacks, PUF characterization attacks, fault injection attack, etc. ); 3) Real-time mitigations solutions such as security via randomization of hardware and its configuration; 4) Peformance improvement (e.g., replacing branch predictions, workload balancing, queue management, etc.) The ability to train robust ML solutions and the existence of a flow that allows translation of the models to logic-based memorization enables us to apply the power of learning to a much wider range of problems, which is otherwise not feasible.