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CHEST 2022 Research Project Abstracts

P5_22: Automated Synthesis and Validation of On-Chip Security Integrity Monitors
Topic Areas: On-Chip Monitoring of ASIC Integrity from Design Through Fabrication and Fielding
Principal investigator: Dr. Ranga R. Vemuri, University of Cincinnati
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Security policies concerning the flow of data in a design can be specified using Information Flow Assertions (IFA) and those concerning the computations performed across time can be specified using Temporal Logic Assertions (TLA). This project aims to use both types of assertions for pre-fab static and dynamic verification as well as post-fab security debug and operational security monitoring using runtime checkers derived from the assertions. The project is divided into three tasks:

• Task 1: Develop methods and tools to compile run-time monitors in synthesizable Verilog for IFA specified in a Sentinel-like notation and TLA specified in the SVA notation. (Year 1)

• Task 2: Develop methods and tools to generate tests to validate the run-time monitors in the presence of a variety of security policy failures. (Year 2)

• Task 3: Demonstrate and evaluate this methodology and tools on significant case-studies and benchmarks to facilitate technology transition. (Both years)

This project was proposed and approved as a 2-year project in 2021. The original project proposal is attached as an appendix for ready reference. Overall project background, motivation, goals, technical approach, tasks and schedule are described in it.

First year of the project commenced on 9/1/2021, coinciding with our academic year. We are in the 8th month since the beginning and are on track to complete the 1st year goals by 8/31/2022.

The rest of this proposal reports the progress achieved so far during the 1st year and describes remaining work to be performed by the team to complete the project in two years as originally proposed.