Introduction

Existing benchmarks for hardware trust applications are drawn from various suites and suffer from one or more of the following limitations: a) too small, b) too old, c) too few, d) designed for other problems, e) not characterized through logic and layout synthesis, and f) have limited applicability to trust problems.  

Accordingly,  this research deals with the construction, compilation, characterization, documentation, and release of suites of  synthetic benchmarks and benchmark generators for various hardware security and trust applications.  

In order to meet feature specifications regarding the number of inputs, outputs, gates, the composition of gate types, connectivity between gates, and the number of logic levels, we generated scalable synthetic benchmark sets. As the various circuit design parameters are changed, we use these benchmarks to experimentally analyze the efficacy of the SAT attack and other attacks against a simple logic encryption scheme. The findings demonstrate the influence of circuit depth and the ratio of xor/xnor gates on the efficacy of the SAT attack, even when a straightforward encryption technique is employed. These findings highlight the value of benchmarking with circuits that are suitable for the application and offer guidelines for secure logic design and trojan insertion.  See the following paper for details:

J. K. Meka, S. Venkatesh and R. Vemuri, "Analysis of the Satisfiability Attack Against Logic Encryption Using Synthetic Benchmarks," 2022 IEEE International Symposium on Smart Electronic Systems (iSES), 2022, pp. 445-450.