Members

Taken at Pranav's lab dinner

Director

    
Director                                    

Dr. Ranga R. Vemuri

ML. 30, University of Cincinnati

Cincinnati, Ohio 45221-0030, USA

Phone: 513-556-7326

Email: Ranga.Vemuri@uc.edu

UC Research Directory: https://researchdirectory.uc.edu/p/vemurir

PhD students

    

    

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Khitam Alatoun

Computer Science and Engineering

Email: alatoukm@mail.uc.edu

Research interests: Hardware Security, Embedded Systems, Cyber-physical systems

        
Haimanti Chakraborty

Haimanti Chakraborty LinkedIn icon

Electrical Engineering

Email: chakrahi@mail.uc.edu

Research interests: Post Silicon Validation, Hardware Security, Digital Design, VLSI

      
Padmaja Bhamidipati

Padmaja Bhamidipati LinkedIn icon

Electrical Engineering

Email: bhamidpa@mail.uc.edu

Research interests: Hardware Security and Trust, Network-on-Chip, Energy Efficiency, Reliability

    
Nikhil Saxena

Nikhil Saxena

Electrical Engineering

Email: saxenanl@mail.uc.edu

Research interests: Hardware Security and Trust, Emerging Devices, SRAMs

   

Christopher Chuvalas

Chris Chuvalas LinkedIn icon

Electrical Engineering

Email: chuvalcm@mail.uc.edu

Research interests: Boolean Satisfiability, Hardware Security, FPGA Architecture, Trust in digital hardware, Algorithm Acceleration

   

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Suriya Srinivasan

Juneeth Kumar Meka LinkedIn icon

Electrical Engineering

Email: mekajr@mail.uc.edu

Research interests: Hardware Security, Logic Encryption, Design Automation, EDA tool development, Machine Learning

Suriya Srinivasan LinkedIn icon

Computer Engineering

Email: srinisy@mail.uc.edu

Research interests: Hardware Security, Model Checking, Satisfiability

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Aparajithan Nathamani Venkatesan

Computer Engineering

Email: nathaman@mail.uc.edu

Research interests: Hardware Security

       
    

MS Students

       

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Satya Amarkant M 

Computer Engineering

Email: marupust@mail.uc.edu

Research interests: Design Automation, Trust in Digital Hardware, Developing Tools and Logic Design

                
PassportSize_Sundarakumar_Muthukumaran.jpg

Sundarakumar Muthukumaran LinkedIn icon

Computer Engineering

Email: muthuksr@mail.uc.edu

Research interests: Hardware Security, Reverse Engineering, FPGA

        
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Kishore Pula  LinkedIn icon

Computer Engineering

Email: pulake@mail.uc.edu

Research interests: Hardware Security, Reverse Engineering, FPGA, Digital Design

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Shrinidhi Venkatesh LinkedIn icon

Electrical Engineering

Emailvenkasd@mail.uc.edu

Research interests: Hardware Security, Logic Encryption, Machine Learning, Design Automation

Sai Suriya

Sai Surya Kannan LinkedIn icon

Electrical Engineering

Emailkannansa@mail.uc.edu

Research interests: Hardware Security and Trust, Boolean Satisfiability, FPGA Architecture

Ram Venketa

Ram Venkat Narayanan LinkedIn icon

Computer Engineering

Emailnarayart@mail.uc.edu

Research interests: Hardware Security

Past Members

PhD students

  • Yasaswy Kasarabada, 2020, "Efficient Logic Encryption Techniques for Sequential Circuits".(Apple)
  • Xiaobang Liu, 2019, "Trace Signal Selection and Restoration Methods for Post-Silicon Validation." (Apple)
  • Suyuan Chen, 2019, "Split Manufacturing: Attacks and Defenses." (Apple)
  • Mike Borowczak, 2013, “Side Channel Attack Resistence: Migrating towards High Level Methods.” (Intel)
  • Annie Avakian, 2012, “Reducing Cache Access Time in Multicore Architectures using Hardware and Software Techniques.” (Synopsys)
  • Hao Xu, 2010, “Run-time Leakage Control in Deep Sub-Micron CMOS Technologies.” (ApacheAnSys)
  • Almitra Pradhan, 2009, “Accurate Analog Synthesis Based on Circuit Matrix Models.” (Synopsys)
  • Angan Das, 2008, “Algorithms for Topology Synthesis of Analog Circuits.” (Intel)
  • Shubhankar Basu, 2008, “Performance Modeling and Optimization Techniques in the Presence of Random Process Variations to Improve Parametric Yield of VLSI Circuits.” (Cadence) 
  • Vijay Sundaresan, 2008, “Architectural Synthesis Techniques for Design of Correct and Secure Digital ICs.” (Intel) 
  • Bala Sethuraman, 2007, “Novel Methodologies for Efficient Networks-On-Chip Implementation on Reconfigurable Devices.” (Mentor Graphics) 
  • Huiying Yang, 2007, “Symbolic Methods for Analog Synthesis,” (Intel) 
  • Jia Xin, 2006, “A Globally Asynchronous and Locally Synchronous FPGA Architecture.” (Mentor Graphics) 
  • Mengmeng Ding, 2006, “Regression Based Analog Performance Macromodeling Techniques and Applications,” Feb 2006. (Analog Devices Crop.) 
  • Renqiu Huang, 2006, “Physical Aware High Level Synthesis and Interconnect for FPGAs,” Feb 2006. (Lattice Semiconductor Corp.) 
  • Amitava Bhadhuri, 2005, “Inductive and Capacitive Coupling Aware Routing Methodology Driven by a Higher Order RLCK Moment Metric.” (Intel Corp) 
  • Jawad Khan, 2005, “Energy Management for Battery-Powered Reconfigurable Computing Platforms and Networks,” (Intel Corp.) 
  • Raoul Badaoui, 2005, “Approaches for Parasitic-Inclusive Symbolic Circuit Representation and Extraction for Synthesis,” (Intel Corp.) 
  • Mukesh Ranjan, 2005, “Automated Layout-Inclusive Synthesis of Analog Circuits Using Symbolic Performance Models,” (Intel Corp.) 
  • Anuradha Agarwal, 2005, “Algorithms for Layout Aware and Performance Model Driven Synthesis of Analog Circuits,” (Intel Corp.) 
  • Glenn Wolfe, 2004, “Performance Macro-modeling techniques for Fast Analog Circuit Synthesis,” (Texas Instruments) 
  • Manish Handa, 2004, “Online Placement and Scheduling Algorithms and methodologies for Reconfigurable Computing Systems,” (Intel Corp.) 
  • Madhubanti Mukherjee, 2004, “Algorithms for Coupling Circuit and Physical Synthesis with High-Level Design-Space Exploration for 2D and 3D Systems,” (Mentor Graphics) 
  • Iyad Ouaiss, Sep 2002. “Hierarchical Memory Synthesis in Reconfigurable Computers”, (Assistant Professor, Lebanese American University, Byblos, Lebanon)
    • Invited participant, NATO Advanced Study Institute on System Level Synthesis, May 1998.
  • Karam Chatha, June 2001. “System Level Co-Synthesis of Transformative Applications for heterogeneous Hardware-Software Architectures”, (Assistant Professor, Arizona State University, Computer Science and Engineering Dept., NSF CAREER Award in 2006.)
    • Best Paper Award recipient at FPL’99.
    • Invited participant, NATO Advanced Study Institute on System Level Synthesis, May 1998.
  • Elena Teica, August 2001. “Formal Correctness and Completeness of a Set of Uninterpreted RTL Transformations”, (Synopsys Inc.)
  • Sree Ganesan, June 2001. “Synthesis of Mixed-Signal Systems Based on Rapid Prototyping”, (Intel Corp.) 
  • Nazanin Mansouri, February 2001. “Automated Correctness Condition Generation for Formal Verification of Synthesized RTL Designs”, (Assistant Professor at Syracuse University, EE&CS Dept.) 
  • Alexa Doboli, August 2000. “Specification and Effective Exploration Methods for High-Level Synthesis of Analog and Mixed-Signal Systems” (Assitant Professor at SUNY at Stonybrook, ECE Dept.)
    • Nominated for Best paper award at Design Automation and Test in Europe Conference, March 1999.
  • Adrian Nunez-Aldana, July 2000, “Performance Estimation for Analog and Mixed-Signal Design Space Exploration” (Assistant Professor at Syracuse University, EE&CS Dept.)
    • Fulbright Scholar, 1995-2000. 
  • Meenakshi Kaul, May 2000, “Optimal and Near-Optimal Temporal Partitioning Techniques for Reconfigurable Computers” (Synopsys)
  • Sriram Govindarajan, March 2000, “High Level Synthesis and Exploration Techniques for Multi-FPGA Reconfigurable Computers” (Cadence)
    • Design Automation Conference, Graduate Mentor, June 1998.
  • Nagu Dhanwada, January 2000, “Constraint Transformation Systems for Synthesis of Analog Systems” (IBM Corp.)
    • Design Automation Conference, PhD Forum, June 1999.
  • Jeff Walrath, Oct 99. “Adaptive Performance Modeling for Configurable VLSI Systems.” (EDAptive Computing Inc.) 
    • Research Associate, ARC Project, ECECS Department, 1997-99.
  • Vinoo Srinivasan, August 99, “Partitioning for FPGA-based Reconfigurable Computers.” (Intel Corp.)
  • Bill Bradley, May 99, “Fixed Point Characterizations of Constraint Satisfaction Problems and Their Use in Performance Verification of VLSI Systems,” (Intel Corp.)
    • SRC Graduate Fellow, 1993-95.
  • Naren Narasimhan, October 1998, “Theorem Proving Guided Development of Formal Assertions and their Embedding in a High-Level VLSI Synthesis System,” (Intel Corp.)
    • Best paper award recipient, International Conference of Computer Design, 1998.
    • Design Automation Conference, Graduate Mentor, June 1996.
  • Srinivas Katkoori, August 1997. “Behavioral Profiling Based High Level Power Estimation Methodologies for VLSI ASIC Synthesis.” (Assistant Professor, University of South Florida, Computer Engineering and Science Dept., Received NSF CAREER Award in 2000.)
    • ECECS Best Thesis Award Runner-Up, June 1998.
    • Design Automation Conference, Graduate Mentor, June 1997.
    • Invited participant, NATO Advanced Study Institute on Low Power Electronics, 1996.
  • Ramanand Mandayam, January 1995, “Performance Modeling of VLSI Systems.” (Motorola Inc., Chicago, IL)
    • Distinguished PhD Dissertation Award Runner-up, VHDL Conference, Fall 1997.
    • Invited participant, NATO Advanced Study Institute on Hardware Description Languages, April 1993.
  • Nand Kumar, October 1994, “High Level VLSI Synthesis for Multichip Designs.” (Research Director, Summit Design Automation, San Jose, CA)
    • ECECS Best Thesis Award, June 1995.
  • Ram Vemuri, July 1994, “Genetic Algorithms for Partitioning, Placement and Layer Assignment for Multichip Modules.” (Intel Corp., Portland, OR)
    • ACM-SIGDA Graduate Fellow, 1990-92.
  • Jay Roy, February 1993, “Parallel Algorithms for High Level Synthesis.” (VP, Summit Design Automation, CA)
    • Best paper award recipient, VHDL Conference, 1991.
  • Kapila Udawatta, March 1992 (co-advisor with Hal Carter), “A Model for Behavioral Synthesis with Exact Timing Specifications.” (Intel Corp, CA)

Visiting Scholars and PhD students

  • Haibo Yi, 2011-13, Visiting PhD Student, School of Computer Science and Engineering, South China University of Technology, Guangzhou, China. Fast Inversion in Small Finite Fields Using Binary Search Trees
  • Col. Dr. Mohamed El-Mehlawy, 2009-2010, Visiting Scholar, Biomedical Engineering Department, Military Technical College, Egyptian Armed Forces, Cairo, Egypt. Test Structures for Digital Designs.
  • Balazs Benyo, Fall 1993-94, Fall-Winter 1994-95 “Test Pattern Generation Based on High Level Hardware Description”
    • Visiting PhD student from Technical University of Budapest, Hungary, under the College of Engineering’s DOE-funded FIPSE project. His second visit in Fall/Winter 1994-95 was funded by the Hungarian Research Foundation. Dr. Benyo received his PhD in 1997 and is currently an Assistant Professor at TUB, Hungary. His dissertation is largely based on the work done in my lab.
  • Csaba Marta, Fall 1993-94, Fall/Winter 1994-95 ”Scan Path Synthesis and Scan Cells in VHDL”
    • Visiting PhD student from Technical University of Budapest, Hungary, under the College of Engineering’s DOE-funded FIPSE project.

MS

  • Shanmukha Murali Achyutha, 2021, SoC Trust Verification Using Assertion-Based and Information Flow Tracking Techniques. (Apple Inc.)
  • Bharath Shankarnarayanan, 2021, Assertion-based Monitors for Run-Time Security Validation. (Synopsys Inc.)
  • Subashree Raja, 2021, Security Architecture and Dynamic Signal Selection in Post-Silicon Validation. (Infineon Technologies)
  • David Luria, 2020, Logic Encryption of Physically Constrained Designs. (Synopsys)
  • Vaishali Muralidharan, 2020, Logic Encryption Using Dynamic Keys. (Cadence)
  • Rishi Bharadwaj Subramanian, 2020, FPGA-based Satisfiability Checking. (Cisco)
  • Rongrong Liu, 2019, A Novel Attack Method Against Split Manufactured Circuits. (Marvell)
  • Suprajaa Tummala, 2019, Heuristics for Signal Selection in Post-Silicon Validation. (Synopsys)
  • Saad Cheema, 2019, Design and Performance Analysis of a Sonar Data Acquisition System. (Intel)
  • Sudheer Ram Thulasi Raman, 2019, Logic Encryption for Sequential Circuits. (Synopsys)
  • Pranav Dharmadhikari, 2018, Hardware Trojan Detection in Sequential Designs. (Cisco)
  • Manasi Joshi, 2018, On Reverse Engineering of Encrypted High-Level Synthesis Designs. (Marvell)
  • Harsh Vamja, 2018, Reverse Engineering of Finite State Machines from Sequential Circuits. (Intel)
  • Richa Agrawal, 2017, FSM State Assignment for Security and Power Optimization. (Synopsys)
  • Sanjana Sekar, 2017, Logic Encryption Methods for Hardware Security. (Cisco)
  • Akhilesh Raju, 2017, Trojan Detection in Hardware Designs.  (Xilinx)
  • Ankita Nayak, 2017, Precision Tunable Hardware Design. (Intel)
  • Renuka Lokhare, 2017, Progressive and Secure Performance Unlocking for Digital Designs. (Intel)
  • Ananathakrishnan Rajendran, 2016, Scalable Hardware Architecture for Memristor Based Artificial Neural Network Systems. (Intel)
  • Prabanjan Komari, 2016, A Novel Simulation Based Approach for Trace Signal Selection in Silicon Debug. (Intel)
  • Harsha Lakkaraju, 2015, DPA Resistant Logic Arrays for Security Applications. (Intel)
  • Mithun Muralidharan Nair, 2014, Statistical Leakage Estimation Using Artificial Neural Net- works. (Intel)
  • Ramesh Nair, 2014, MITH-Dyn: A Multi Vth Dynamic Logic Design Style Using Mixed Mode FinFETs. (Intel)
  • Lava Kumar Atluri, 2014, Design Automation Flow using Library Adaptation for Variation Aware Logic Synthesis. (Intel)
  • Shaun Peter, 2014, A Performance Driven Placement System Using an Integrated Timing Analysis. (Synopys)
  • Tuhin Mukherjee, 2014, Cluster Shaping: A novel optimization technique for large scale VLSI placement. (Intel)
  • Nakul Tirumalai, 2014, LCPlace: A Novel VLSI Placement Methodology based on large cluster formation. (Synopsys)
  • Fan Zhang, 2013, Parallelization of Negotiated Congestion Algorithm in FPGA Routing. (Xilinx)
  • Antarpreet Singh Manchada, 2013, Design Methodology for Differential Power Analysis Re- sistant Circuits. (Intel)
  • Venkat Krishnan Balasubramaniyan, 2012, Design Automation Flow for Voltage Adaptive Light Vth Hopping for Leakage Minimization in Sequential Circuits. (Intel)
  • Greg Mefford, 2012, Side Channel Analysis Research Framework (SCARF). (L3 Corp.)
  • Manoj Chakravarthy, 2012, BDD Based Synthesis Flow for Design of DPA Resistant Cryptographic Circuits. (Intel)
  • Aditi Vijaykumar, 2012, DPA Resistance of Cryptographic Circuits Considering Temperature and Process Variations. (Synopsys)
  • Aishwariya Pattabhiraman, 2011, Heterogeneous Cache Architecture in Network-on-Chips. (Intel)
  • Amayika Panda, 2011, A Novel Configurable Benchmarking System for Multi-core Architectures. (Intel)
  • Natwar Agrawal, 2011, A Generic Synthesizable HDL Platform for Network on Chip(GSHNoC). (Xilinx)
  • Lakshmi Narasimhan Ramakrishnan, 2011, SDMLp - Secure Differential Multiplexer Logic: Logic Design for DPA-Resistant Cryptographic Circuits. (Synopsys)
  • Ajaay Ravi, 2011, Run-Time Active Leakage Control Mechanism based on a Light Threshold Voltage Hopping Technique (LITHE). (Intel)
  • Suryanarayana Pendala, 2010, Techniques for Variation Aware Modeling in Static Timing Analysis of Integrated Circuits. (Intel)
  • Romana Fernandes, 2010, Estimation and Optimization of Leakage Power in the Presence of Process Variations. (Intel)
  • Jonathan Nafziger, 2010, A Novel Cache Migration Scheme in Networks-on-Chip. (Texas Instruments)
  • Pritesh Johari, 2009, “Distributed Decap-Padded Standard Cell Based On-Chip Voltage Drop Compensation Framework.” (Intel)
  • Suman Kasam, 2008, “Formal verification of time constrained UAV task allocation using model-checking.” (Qualcom)
  • Balaji Kommineni, 2008, “Spline center and range regression technique and its application to variation aware performance macromodeling of analog circuits.” (Sun Microsystems)
  • Manoj Raghupathy, 2008, “Switch Level Simulation in the Presence of Uncertainties.” (Ca- dence)
  • Priyanka Thakore, 2007, “Development of process variation tolerant standard cells.” (Intel).
  • Srividhya Rammohan, 2007, “Reduced complementary dynamic and differential cmos logic: a design methodology for DPA resistant cryptographic circuits.”
  • Reno Massarini, 2007, “Power - aware mobile sensor networks with reconfigurable computing nodes ,” (Motorola)
  • Jiangping Yan, 2006, “A Tiled FPGA Architecture for Power-Aware Computations,” (Intel)
  • Ritochit Chakraborty, 2006, “Symbolic Time Domain Analysis Based on Symbolic Symbolic Newton-Iteration Algorithm for Pole Extraction.” (Univ. Washington)
  • Prasun Bhattacharya, 2006, “Comparison of Single Port and Multi-Port Memories with Con- temporary Buses on FPGAs,” (Nvidia)
  • Akhil Krishnan, 2005, “Hardware Implementations of Crypto Algorithms,” (Sun Microsystems)
  • Vikas Vijay, 2004, “A Top-Down Methodology for Synthesis of RF Circuits,” (Freescale Semi- conductor)
  • Jayanti Rajagoplan, 2004, “Implementation of a Dynamically Reconfigurable Asynchronous Programmable Logic (DRAPL) Architecture,” (Intel Corp.)
  • Vipul Patel, 2004, “Behavioral simulation and synthesis environment for continuous-time single-loop single-bit baseband delta-sigma analog-to-digital modulators.” (Air Force Re- search Laboratory)
  • Shyamsundar Balasubramanian, 2004, “A Novel Methodology for Modeling Performance Parameters of Analog Circuits,” (Intel Corp.)
  • Sunder Kankipati, February 2004, “Macro Model Generation for Synthesis of Analog and Mixed-Signal Circuits.” (Intel Corp.)
  • Tao Chen, February 2004, “Multi-FPGA Partitioning Using Simulated Annealing,” (Ampac. Inc.)
  • Veena Yelamanchili, October 2003, “A Simulation and Performance Estimation System for Analog and Mixed Signal Systems.”
  • Srinivas Muppidi, July 2003, “Genetic Algorithms for Multi-Objective Partitioning.”
  • Hemanth Sampath, May 2003, “A Module Generation Environment for Mixed Signal Circuits.” (NeoLinear Inc.)
  • Jawad Khan, May 2002, “The iPACE Portable Real-Time Adaptive Computer”. (continuing for PhD)
  • Manish Handa, May 2002, “A Design Environment for Dynamic Partial Reconfiguration for the iPACE Adaptive Computer”. (continuing for PhD)
  • Siva Subramanyam, April 2002, “Applications of Satisfiability in Synthesis of Reconfigurable Computers”. (Xilinx Corp.)
  • Srinivasan Dasasatyan, May 2001, “Synthesis of Virtual Pipelines on Virtex-Based FPGAs”. (Xilinx Corp.)
  • Amit Kasat, April 2001, “Memory Synthesis for FPGA-Based Reconfigurable Computers”. (Xilinx Corp.)
  • Priya Vattyam, March 2000, “Performance Modeling Methodologies Using PDL+ and ARC,” (Sun Microsystems)
  • Abhijit Ghosh, March 2000, Formal verification of analog designs. “Formal Verification of Synthesized Analog and Mixed Signal Designs.” (Cadence)
  • Sujatha Sundararaman, February 2000, “Application Specific Macro Based Synthesis,” (LSI Logic)
  • Awartika Pandey, Feb 2000, Partitioning for adaptive systems. “Behavior Level Temporal Partitioning and Design Space Exploration for Reconfigurable Architectures.” (Synplicity)
  • Satish Ganesan, Jan 2000, “Temporal Partitioning and Synthesis for Partially Reconfigurable Architectures,” (Xilinx Inc.)
  • Preetham Lakshmikantan, Oct 1999, “Partitioning of Behavioral Specifications for Reconfigurable Multi-FPGA Architectures,” (Cadence)
  • Shankarram Radhakrishnan, April 1999, “Interconnect Synthesis for Reconfigurable Computers.” (Intel Corp.)
  • Paul Campisi, April 1998, “A CMOS Analog Cell Library for Analog Synthesis Systems.” (Sun Microsystems)
  • Anurag Gupta, November 1997, Area and Delay Estimation for Behavior Level VLSI ASIC Synthesis.” (Digital Equipment Corp, MA)
  • Viresh Paruthi, November 1997, “Automatic Datapath Abstraction for Verification of Large Scale Designs.” (IBM, Austin, TX)
  • R. Arun Kumar, November 1997, “WAVES testset Compilation for Designs with Boundary Scan.” (Cadence, MA)
  • Jeff Walrath, October 1997, “Partial Evaluation of Performance Models and Its Applications.” (Research Associate, ECECS Department, University of Cincinnati and PhD Candidate)
  • Michael C. Doll, August 1997, “WAVES Testset Compilation for Synthesized Designs.” (Motorola, IL)
  • Madhavi Vootukuru, July 1997, “Performance Estimation and Partitioning of VHDL Models for FPGA Implementation.” (Digital Equipment Corp.)
  • Vijay Meduri, September 1994, “Automatic Generation of Performance Models in VHDL from PDL Specifications.” (LSI Logic Corp., San Jose, CA)
  • Ravi Kalyanaraman, August 1993, “Behavioral Test Vector Generation in WAVES/VHDL Environment.” (Intel Corp., AZ.) ECECS Best MS Thesis Award.
  • Jeff Kehl, June 1993, “XPARA: A CAD Tool for Radiation Tolerant VLSI Design.” (Intel Corp., AZ)
  • Praveen Sinha, December 1992, “Design and Evaluation of Module Generator Libraries for VHDL-Centered High-Level Synthesis.” (Intel Corp, AZ)
  • Subba Rao, November 1992, “Boundary-Scan Test Structure Compiler in a Multicomponent Synthesis Environment.” (LSI Logic Corp.)
  • Paddy Mamtora, Oct 1992, “Functional Validation of a High-Level Synthesis System through Simulation and Test Bench Compilation.” (Mentor Graphics Corp.)
  • Raghu Vutukuru, August 1992, “Test Bench Compilation for Synthesized Multicomponent Designs.” (National Semiconductor, San Jose, CA)
  • Ning Ren, Feb 1992, “Distribution of Existing Digital System Simulators on a Network of Workstations Based on a Scheduler-Server Model.” (Lexmark Peripherals Inc., subsidiary of IBM Corp.)
  • Robert Hoffa, General Electric Co., Dec 1991, “Constraint-Driven Selection of Fuel Injection Patterns for a Dry-Low-NOx Combustor Using Genetic Algorithms.” (General Motors Co., Detroit) F.O. MacFee Award for Best MS Thesis and Coursework.
  • Rajiv Dutta, Oct 1991, “Distributed Design-Space Exploration for High-Level Synthesis Systems.” (Summit Design Automation, San Jose, CA)
  • James Koch, April 1991, “Computerized Data Acquisition Trending System (CATS).” (General Electric Co.)
  • Anuradha Sridhar, Feb 1991, “Techniques for Precondition Verification of Register-Level Design Transformations”.

MEng

  • Shruthi Arun, Capacitive Analog Trojans. (2017) Cypress Semiconductor.
  • Meera Viswanathan, Post Silicon Debug Methods. (2015) Synopsys Inc.
  • Ujwal Ramesh, Analytical Clustering and Partitioning. (2014) Intel Corp.
  • Shambhavi Kulkarni, Layout of Test Structures. (2010) Intel Corp.