University of Cincinnati

College of Engineering and Applied Science  |   Electrical Engineering and Computer Science Department
Digital Design Environments Laboratory

Publications

Listed below are all publications written by one or more members of DDEL. To cite any paper, DO NOT copy the list item. Instead copy the paper title and use citation generators (like Google Scholar, Citation Machine, etc.) to generate citations.
  1. Yasaswy Kasarabada, Vaishali Muralidharan and Ranga Vemuri, SLED: Sequential Logic Encryption Using Dynamic Keys, 2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS). IEEE, 2020.
  2. Suprajaa Tummala, Xiaobang Liu and Ranga Vemuri, Signal Selection Heuristics for Post-Silicon Validation, 2020 21st International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, USA, 2020.
  3. David Luria, Yasaswy Kasarabada and Ranga Vemuri, Constraint-Directed Logic Encryption, Government Microcircuit Applications & Critical Technology Conference (GOMACTech), San Diego, CA, USA, 2020.
  4. Yasaswy Kasarabada and Ranga Vemuri, StateLock: State Transition Based Logic Locking for Sequential Circuits, 2020 33rd International Conference on VLSI Design and 2020 19th International Conference on Embedded Systems (VLSID), Bengaluru, India, 2020.
  5. Yasaswy Kasarabada, David Luria and Ranga Vemuri, Trust in IoT Devices: A Logic Encryption Perspective, 2nd IFIP International Internet of Things (IoT) Conference, Tampa, FL, USA, 2019.
  6. Richa Agrawal, Ranga Vemuri and Mike Borowczak, A State Machine Encoding Methodology Against Power Analysis Attacks, Journal of Electronic Testing, Springer, 2019.
  7. [Invited Paper] Harsh Vamja, Richa Agrawal and Ranga Vemuri, Non-Invasive Reverse Engineering of Finite State Machines Using Power Analysis and Boolean Satisfiability, 62nd IEEE International Midwest Symposium on Circuits and Systems (MWCAS), Dallas, TX, 2019.
  8. Nikhil Gohil and Ranga Vemuri, Automated Synthesis of Differential Power Attack Resistant Integrated Circuits, IEEE National Aerospace & Electronics Conference (NAECON), Dayton, OH, USA, 2019.
  9. Yasaswy Kasarabada, Sudheer Ram Thulasi Raman and Ranga Vemuri, Deep State Encryption for Sequential Logic Circuits, 2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Miami, FL, USA, 2019.
  10. Suyuan Chen and Ranga Vemuri, Exploiting Proximity Information in a Satisfiability Based Attack Against Split Manufactured Circuits, 2019 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), McLean, VA, USA, 2019.
  11. Mike Borowczak and Ranga Vemuri, Mitigating Information Leakage During Critical Communication using S*FSM, IET Computers & Digital Techniques, 2019.
  12. Sanjana Sekar and Ranga Vemuri, Robust Logic Obfuscation for Trusted Design Synthesis, Government Microcircuit Applications & Critical Technology Conference (GOMACTech), Miami, FL, USA, 2019.
  13. Yasaswy Kasarabada, Suyuan Chen and Ranga Vemuri, On SAT-Based Attacks On Encrypted Sequential Logic Circuits, 2019 20th International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, USA, 2019.
  14. Xiaobang Liu and Ranga Vemuri, Assertion Coverage Aware Trace Signal Selection in Post-Silicon Validation, 2019 20th International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, USA, 2019.
  15. Richa Agrawal, Mike Borowczak and Ranga Vemuri, A State Encoding Methodology for Side-Channel Security vs. Power Trade-off Exploration, 2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID), Delhi NCR India, 2019.
    • Best Paper Award Nomination, 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID), Delhi NCR India, 2019.
  16. Suyuan Chen and Ranga Vemuri, Reverse Engineering of Split Manufacturing Sequential Circuits using Satisfiability Checking, 2018 IEEE International Conference on Computer Design (ICCD), Orlando, FL, 2018.
  17. Suyuan Chen and Ranga Vemuri, On the Effectiveness of the Satisfiability Attack on Split Manufactured Circuits, Very Large Scale Integration (VLSI-SoC), 2018 IFIP/IEEE International Conference on. IEEE, 2018.
  18. Pranav Dharmadhikari, Akhilesh Raju and Ranga Vemuri, Detection of Sequential Trojans in Embedded System Designs Without  Scan Chains. VLSI (ISVLSI), 2018 IEEE Computer Society Annual Symposium on. IEEE, 2018.
  19. Xiaobang Liu and Ranga Vemuri, Fast Heuristics for near-optimal Signal Restoration in Post-Silicon Validation. VLSI (ISVLSI), 2018 IEEE Computer Society Annual Symposium on. IEEE, 2018.
    • Best Paper Award Nomination, IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2018.
  20. Suyuan Chen and Ranga Vemuri. 2018. Improving the Security of Split Manufacturing Using a Novel BEOL Signal Selection Method. In GLSVLSI ’18: 2018 Great Lakes Symposium on VLSI, May 23–25, 2018, Chicago, IL, USA.
  21. Richa Agrawal and Ranga Vemuri, On State Encoding Against Power Analysis Attacks for Finite State Controllers, in Hardware Oriented Security and Trust (HOST), 2018 IEEE International Symposium on.IEEE, 2018, pp. 181–186.
  22. Xiaobang Liu and Ranga Vemuri, Combined Inference and Satisfiability Based Methods for Complete Signal Restoration in Post-Silicon Validation, 2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID), Pune, India, 2018, pp. 416-421.
    • Received the Best Paper award at the conference.
  23. Ankita Manjunath Nayak and Ranga Vemuri, A Secure Tunable-Precision Architecture for Image Processing Applications, 2018 IEEE International Conference on Consumer Electronics (ICCE), Las Vegas, NV, USA, 2018 (pp. 1-5).
  24. Renuka Lokare and Ranga Vemuri, Progressive and Secure Performance Unlocking for Digital Integrated Circuits, 2018 IEEE International Conference on Consumer Electronics (ICCE), Las Vegas, NV, USA, 2018 (pp. 1-6).
  25. Xiaobang Liu and Ranga Vemuri, Effective Signal Restoration in Post-Silicon Validation, 2017 IEEE International Conference on Computer Design (ICCD), Boston, MA, 2017, pp. 169-176.
  26. Haibo Yi, Shaohua Tang, Ranga Vemuri, Fast Inversions in Small Finite Fields by Using Binary Trees, The Computer Journal 59(7): 1102-1112, 2016.
  27. Prabanjan Komari and Ranga Vemuri, A Novel Simulation Based Approach for Trace Signal Selection in Silicon Debug, Proc. IEEE International Conference on Computer Design, pp. 193-200, Oct 2016.
  28. Ananthakrishnan Ponnileth and Ranga Vemuri, Scalable Hardware Architecture for Memristor Based Artificial Neural Network Systems, Workshop on Hardware and Algorithms for Learning On-a-chip (HALO), 2016.
  29. Ramesh Nair and Ranga Vemuri, MITH-Dyn : A Multi Vth Dynamic Logic Design Style Using Mixed Mode FinFETs, 27th IEEE International Conference on Systems on Chip, Sep 2014, 140-145.
  30. Mike Borowczak and Ranga Vemuri, Enabling Side Channel Secure FSMs in the presence of Low Power Requirements, IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2014, 232-235.
  31. Mike Borowczak and Ranga Vemuri, Secure Controllers: Requirements of S*FSM(Link), IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS), 2013.
  32. Venkat Balasubramaniyan, Hao Xu and Ranga Vemuri, Design Automation Flow for Voltage Adaptive Optimum Granular LITHE for Sequential Circuits, IEEE SOCC 2013, 355-360.
  33. Annie Avakian, Natwar Agrawal, Ranga Vemuri: Reconfigurable Multicore Architecture for Dynamic Processor Reallocation. ARC 2012: 329-334.
  34. Borowczak, M.; Vemuri, R., S*FSM: A Paradigm Shift for Attack Resistant FSM Designs and Encodings, BioMedical Computing (BioMedCom), 2012 ASE/IEEE International Conference on, vol., no., pp.96,100, 14-16 Dec. 2012
    • Also as, Redefining and Integrating Security Engineering (RISE), 2012 ASE International Conference on Cyber Security, pp. 651-655, 14-16 Dec 2012.
  35. Lakshmi Narasimhan Ramakrishnan, Manoj Chakkaravarthy, Antarpreet Singh Manchanda, Mike Borowczak, Ranga Vemuri: SDMLp: On the use of complementary Pass transistor Logic for design of DPA resistant circuits. HOST 2012: 31-36.
  36. Aishwariya Pattabiraman, Annie Avakian, Ranga Vemuri: A Heterogeneous Cache Distribution with Reconfigurable Interconnect. IPDPS Workshops 2012: 271-276.
  37. Amayika Panda, Annie Avakian, Ranga Vemuri: Configurable workload generators for multicore architectures. SoCC 2011: 179-184.
  38. Hao Xu, Ranga Vemuri, Wen-Ben Jone, Dynamic Characteristics of Power Gating During Mode Transition, IEEE Trans. VLSI Syst. 19(2): 237-249 (2011).
  39. Hao Xu, Wen-Ben Jone, Ranga Vemuri, Aggressive Runtime Leakage Control Through Adaptive Light-Weight Vth HoppingWith Temperature and Process Variation, IEEE Trans. VLSI Syst. 19(7): 1319-1323 (2011).
  40. Hao Xu, Wen-Ben Jone, Ranga Vemuri, Tuning Vth Hopping for Aggressive Runtime Leakage Control, J. Low Power Electronics 6(3): 447-456 (2010)
  41. Hao Xu, Wen-Ben Jone, Ranga Vemuri: Stretching the limit of microarchitectural level leakage control with Adaptive Light-Weight Vth Hopping. ICCAD 2010: 632-636
  42. Hao Xu, Ranga Vemuri, Wen-Ben Jone: Current shaping and multi-thread activation for fast and reliable power mode transition in multicore designs. ICCAD 2010: 637-641
  43. Annie Avakian, Jon Nafziger, Amayika Panda, Ranga Vemuri: A reconfigurable architecture for multicore systems. IPDPS Workshops 2010: 1-8
  44. Jon Nafziger, Annie Avakian, Ranga Vemuri: A prediction-based, data Migration Algorithm for hybrid Architecture NoC systems. SoCC 2010: 435-440
  45. Hao Xu, Wen-Ben Jone, Ranga Vemuri: Novel Vth Hopping Techniques for Aggressive Runtime Leakage Control. VLSI Design 2010: 51-56
  46. Romana Fernandes, Ranga Vemuri, Accurate estimation of vector dependent leakage power in the presence of process variations. ICCD 2009: 451-458.
  47. Hao Xu, Ranga Vemuri and Wen-Ben Jone, Selective Light Vth-Hopping (SLITH): Bridging the Gap Between Run-Time Dynamic and Leakage Power Reduction, Design Automation and Test and in Europe (DATE), April 2009.
  48. Hao Xu, Ranga Vemuri and Wen-Ben Jone, Temporal and spatial idleness exploitation for optimal-grained leakage control, International Conf. on Computer-Aided Design (ICCAD) 2009, pp. 468-473, 2009.
  49. A. Das and R. Vemuri, A Graph Grammar Based Approach to Automated Multi-Objective Analog Circuit Design, in Proc. of Design, Automation & Test in Europe (DATE), April 2009.
  50. A. Das and R. Vemuri, Fuzzy Logic Based Guidance to Graph Grammar Framework for Automated Analog Circuit Design, in Proc. of International Conference on VLSI Design (VLSID), pp. 445-450, January 2009.
  51. S. Basu, B. Kommineni and R. Vemuri, Variation-Aware Macromodeling and Synthesis of Analog Circuits Using Spline Center and Range Method and Dynamically Reduced Design Space, 22nd International Conference on VLSI Design, pp. 433-438, January 2009.
  52. Almitra Pradhan, Ranga Vemuri, Efficient Synthesis of a Uniformly Spread Layout Aware Pareto Surface for Analog Circuits, 22nd International Conference on VLSI Design, January 2009.
  53. Almitra Pradhan and Ranga Vemuri, Accurate Performance Estimation using Circuit Matrix Models in Analog Circuit Synthesis, Invited book chapter, IFIP Series on VLSI-SoC, Springer 2008.
  54. Hao Xu, Wen-Ben Jone and Ranga Vemuri, Accurate Equivalent Energy Breakeven Time Estimation for Power Gating, International Conference on Computer Aided Design (ICCAD), pp. 161-168, Nov 2008.
  55. Hao Xu, Ranga Vemuri, Wen-Ben Jone, Run-Time Active Leakage Reduction by Power Gating and Reverse Body Biasing: An Energy View, International Conference on Computer Design (ICCD), pp. 618-626, Oct 2008.
  56. Hao Xu, Ranga Vemuri and Wen-Ben Jone, Dynamic Virtual Ground Voltage Estimation for Power Gating, International Symposium on Low Power Electronics and Design (ISLPED), pp. 27-32, Aug 2008. (Best Paper Award at the Conference among about 75 papers selected for presentation.)
  57. V. Sundaresan, S. Rammohan and R. Vemuri, Defense against Side-Channel Power Analysis Attacks in Microelectronic Systems, in Proc. of the 2008 IEEE National Aerospace and Electronics Conference (NAECON 2008), July 16-18, 2008.
  58. R. Vemuri, M. Borowczak, A. Avakian, Safety Centric Design of Distributed Embedded Avionics, in Proc. of the 2008 IEEE National Aerospace and Electronics Conference (NAECON 2008), pp. 293-299, July 16-18, 2008.
  59. Almitra Pradhan, Ranga Vemuri, A Circuit Matrix Model Based Layout Aware Method for Module Selection and Synthesis of Analog Circuits, 18th Great Lakes Symposium on VLSI, May 2008.
  60. Almitra Pradhan, Ranga Vemuri, Fast Analog Circuit Synthesis Using Sensitivity Based Near Neighbor Searches, 11th Conference on Design Automation and Test in Europe, March 2008.
  61. A. Das and R. Vemuri, A Self-Learning Optimization Technique for Topology Design of Computer Networks, in Proc. of European Workshop on the Application of Nature-inspired Techniques to Telecommunication Networks and other Connected Systems (EvoCOMNET), pp. 38-51, March 2008. (Best Paper Award at the conference.)
  62. S. Basu, B. Kommineni and R. Vemuri, Variation Aware Spline Center and Range Modeling for Analog Circuit Performance, 9th International Symposium on Quality Electronic Design (ISQED), pp. 17-19, March, 2008.
  63. Almitra Pradhan, Ranga Vemuri, On the Use of Hash Tables for Efficient Analog Circuit Synthesis, 21st Conference on VLSI Design, January 2008.
  64. S. Basu, K. Balaji and R. Vemuri, Mismatch aware analog performance macromodeling using spline center and range regression on adaptive samples, International Conference On VLSI Design, pp. 287-293, 2008.
  65. A. Das and R. Vemuri, ATLAS: An Adaptively formed Hierarchical Cell Library based Analog Synthesis Framework, in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2542-2545, May 2008.
  66. A. Das and R. Vemuri, Topology Synthesis of Analog Circuits based on Adaptively Generated Building Blocks, in Proc. of IEEE/ACM Design Automation Conference (DAC), pp. 44-49, June 2008.
  67. S. Rammohan, V. Sundaresan and R. Vemuri, Reduced Complementary Dynamic and Differential Logic: A CMOS Logic Style for DPA-resistant Secure IC Design, in Proc. of the 21st Conference on VLSI Design (VLSI Design 2008), January 4-8, 2008.
  68. Almitra Pradhan, Ranga Vemuri, Regression based Circuit Matrix Models for Accurate Performance Estimation of Analog Circuits, 15th IFIP VLSI-SOC Conference, October 2007, p48-53.
  69. A. Das and R. Vemuri, GAPSYS: A GA-based Tool for Automated Passive Analog Circuit Synthesis, in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), May 2007, pp. 2702-2705.
  70. A. Das and R. Vemuri, An Automated Passive Analog Circuit Synthesis Framework using Genetic Algorithms, in Proc. of IEEE International Symposium on VLSI (ISVLSI), March 2007, pp. 145-152.
  71. S. Basu and R. Vemuri, Process Variation and NBTI Tolerant Standard Cells to Improve Parametric Yield and Lifetime of Integrated Circuits, IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 291-298, March 2007.
  72. Bala Sethuraman and Ranga Vemuri, Power Variations of MultiPort Routers in an Application-Specific NoC Design: A Case Study, 25th International Conference on Computer Design (ICCD), October 2007.
  73. Bala Sethuraman and Ranga Vemuri, Multicasting based Topology Generation and Core Mapping for Power Efficient Networks-On-Chip, IEEE/ACM-SIGDA International Symposium on Low Power Electronics and Design (ILPED 2007), August 2007.
  74. Vijay Sundaresan, Srividhya Ramamohan and Ranga Vemuri, Power Invariant Secure IC Design Methodology using Reduced Complementary Dynamic and Differential Logic, in Proc. Of the IFIP International Conference on VLSI, Oct 2007.
  75. S. Basu, Priyanka Thakore and R. Vemuri, Process variation tolerant standard cell library development using reduced dimension statistical modeling and optimization techniques, International Symposium on Quality Electronic Design, pp. 814-820, 2007.
  76. S. Basu, B. Kommineni and R. Vemuri, A Spline Based Regression Technique on Interval Valued Noisy Data, Sixth International Conference on Machine Learning and Applications (ICMLA), pp. 13-15, Dec 2007.
  77. N. Dhanwada, A. Doboli, A. Nunez, R. Vemuri, Hierarchical Constraint Transformation based on Genetic Optimization for Analog System Synthesis, Integration, the VLSI Journal, Elsevier, vol. 39, no. 3, pp. 269-607, March 2006.
  78. Bala Sethuraman and Ranga Vemuri, OptiMap: A Tool for Generating Efficient NoC Architectures using Multi-Port Routers for FPGAs, Design Automation and Test in Europe (DATE) Conference, March 2006.
  79. Vijay Sundaresan and Ranga Vemuri, A Novel Approach to Performance Oriented Datapath Allocation and Floorplanning, IEEE CS International Symposium on VLSI, March 2006.
  80. H. Yang, R. Vemuri, Effficient Temperature Dependent Symbolic Sensitivity Analysis and Symbolic Performance Evaluation in Analog Circuit Synthesis, Design Automation and Test in Europe (DATE) Conference, March 2006.
  81. Vijay Sundaresan, Rajesh Radhakrishnan, S. Siva and Ranga Vemuri, Symbolic Verification of Synthesized RTL Designs using Uninterpreted RTL Transformations and Boolean Satisfiability, IEEE Midwest Symposium on Circuits and Systems, Aug 2005.
  82. Amitava Bhaduri and Ranga Vemuri, Moment-driven coupling-aware routing methodology, ACM Great Lakes Symposium on VLSI 2005, pp. 390-395.
  83. Amitava Bhaduri and Ranga Vemuri, Inductive and Capacitive Coupling Aware Routing Methodology Driven by a Higher Order RLCK Moment Metric, DATE 2005, pp. 922-923.
  84. Anuradha Agarwal and Ranga Vemuri, Hierarchical Performance Macromodels of Feasible Regions for Synthesis of Analog and RF Circuits, ACM/IEEE International Conference on Computer-Aided Design (ICCAD), Nov 2005.
  85. Anuradha Agarwal and Ranga Vemuri, Layout-Aware RF Circuit Synthesis Driven by Worst Case Parasitic Corners, IEEE International Conference on Computer Design (ICCD), October 2005.
  86. Ritochit Chakraborty, Mukesh Ranjan and Ranga Vemuri, Symbolic Time-Domain Behavioral and Performance Modeling of Linear Analog Circuits Using an Efficient Symbolic Newton-Iternation Algorithm for Pole Extraction, 18th International Conference on VLSI Design, January 2006.
  87. Mukesh Ranjan, Ritochit Chakraborty and Ranga Vemuri, Parasitic-Aware Hierarchical Symbolic Performance Modeling for Layout-Inclusive Synthesis of Large Analog Circuits, Behavior Modeling and Simulation Conference (BMAS), Sep. 2005.
  88. Mengmeng Ding and Ranga Vemuri, Efficient Analog Performance Macromodeling via Sequential Design Space Decomposition, 18th International Conference on VLSI Design, January 2006.
  89. J. Xin and R. Vemuri, CAD Tools for a Globally Asynchronous, Locally Synchronous FPGA Architecture, 18th International Conference on VLSI Design, January 2006.
  90. Amit Bhadhuri and Ranga Vemuri, Parasitic Aware Routing Methodology Based on Higher Order RLCK Moment Metrics, 18th International Conference on VLSI Design, January 2006. (Nominated by the program committee for the Best Paper Award, among the nearly 100 papers presented at the conference.)
  91. M. Ding and R. Vemuri, Analog Macromodeling: A Combined Feasibility and Performance Macromodel for Analog Circuits, Proc. 42nd Design Automation Conference, June 2005.
  92. A. Agarwal, G. Wolfe and R. Vemuri, Accuracy Driven Performance Macromodeling of Feasible Regions During Synthesis of Analog Circuits, Proc. 15th ACM Great Lakes Symposium on VLSI, April 2005.
  93. A. Bhaduri and R. Vemuri, Moment-Driven Coupling-Aware Routing Methodology, Proc. 15th ACM Great Lakes Sympoium on VLSI, April 2005.
  94. B. Sethuraman, P. Bhattacharya, J. Khan and R. Vemuri, LiPaR: A Light-Weight Parallel Router for FPGA-Based Newtorks on Chip, Proc. 15th ACM Great Lakes Symposium on VLSI, April 2005.
  95. Jawad Khan and Ranga Vemuri, Energy Management for Battery Powered Reconfigurable Computing Platforms, IEEE Transactions on VLSI Systems, vol. 14, no. 2, pp. 135-147, Feb 2005.
  96. M. Handa and R. Vemuri. Hardware assisted two dimensional ultra fast placement. Invited paper, special issue on Advances in Reconfigurable Architectures, International Journal of Embedded Systems, vol. 1, no. 3/4, pp. 291-299, 2005.
  97. F. Badaoui and R. Vemuri. Multi-placement structures for fast and optimized placement in analog circuit synthesis. In Design Automation and Test in Europe, DATE 2005, 2005.
  98. M. Ding and R. Vemuri. An active learning scheme using support vector machines for analog circuit feasibility classification. In Proceedings of the 18th International Conference on VLSI Design, 2005.
  99. M. Ding and R. Vemuri. A two-level modeling approach to analog circuit performance macromodeling. In Proceedings of Design, Automation and Test in Europe Conference and Exhibition, 2005.
  100. M. Ding, G. Wolfe and R. Vemuri. An error-driven adaptive grid refinement algorithm for automatic generation of analog circuit performance macromodels. In Proceedings of the Asian and South Pacific Design Automation Conference, 2005.
  101. R. Huang and R. Vemuri, Sensitivity Analysis of a Cluster-Based Interconnect Model for FPGAs, IEEE International Symposium on VLSI, 2005.
  102. H. Yang, A. Agarwal and R. Vemuri, Fast Analog Circuit Synthesis Using Multiparameter Sensitivity Analysis Based on Element-Coefficient Diagrams, IEEE International Symposium on VLSI, 2005.
  103. M. Handa and R. Vemuri. An efficient algorithm for finding empty space for online fpga placement. In Proceedings of the 41st Design Automation Conference, pages 960 – 965, 2004.
  104. M. Handa and R. Vemuri. An integrated online scheduling and placement methodology. In Proceedings of the Field Programmable Logic and its Applications, pages 444–453, 2004.
  105. M. Handa and R. Vemuri. On area fragmentation of reconfigurable operating systems. In Engineering of Reconfigurable Systems and Algorithms, 2004.
  106. A. Bhaduri, V. Vijay, A. Agarwal, R. Vemuri, B. Mukherjee, P. Wang and A. Pacelli. Parasitic-Aware Synthesis of RF LNA Circuits considering Quasi-Static Extraction of Inductors and Interconnects. In 47th Midwest Symposium on Circuits and Systems, pages 1211 - 1214, July 2004.
  107. A. Agarwal, H. Sampath, V. Yelamanchili and R. Vemuri. Fast and accurate parasitic capacitance models for layout-aware synthesis of analog circuits. In Proceedings of the 41st annual Design Automation Conference, pages 145–150. ACM Press, 2004.
  108. R. Huang, M. Handa and R. Vemuri. A hybrid interconnect architecture for dynamically reconfigurable fpgas. In International conference on Field-Programmable Logic and its Applications, Aug 2004.
  109. R. Huang and R. Vemuri. Analysis and evaluation of a hybrid interconnect structure for fpgas. In IEEE/ACM International Conference on Computer Aided Design, Nov 2004.
  110. R. Huang and R. Vemuri. The property and sensitivity of a cluster-based interconnect structure for fpgas. In IEEE international conference on field programmable technology, Dec 2004.
  111. R. Huang and R. Vemuri. On-line synthesis for partially reconfigurable fpgas. In IEEE 18th international conference on VLSI Design, Jan 2005.
  112. X. Jia, J. Rajagopalan and R. Vemuri. A dynamically reconfigurable asynchronous fpga architecture. In Proc. Field Programmable Logic and its applications, Aug. 2004.
  113. X. Jia and R. Vemuri. A design methdology for self-timed event logic pipelines. In Proc. VLSI’04, 18 Joint Int. Conf. CS and CE, Jun. 2004.
  114. X. Jia and R. Vemuri. Using gals architecture to reduce the impact of long wire delay on fpga performance. In Proc. Asia South Pacific Design Automation Conf., Jan. 2005.
  115. J. Khan, J. Rajagopalan, R. Huang and R. Vemuri. A Portable Face Recognition System using Reconfigurable Hardware. In ERSA04: The International Conference on Engineering of Reconfigurable Systems and Algorithms, pages 213–217, LasVegas, Nevada, June 2004. C.S.R.E.A. Press.
  116. J. Khan, B. Sethuraman and R. Vemuri. A Power-Performance Tradeoff Methodology for Portable Reconfigurable Platforms. In ERSA04: The International Conference on Engineering of Reconfigurable Systems and Algorithms, pages 33–37, LasVegas, Nevada, June 2004. C.S.R.E.A. Press.
  117. J. Khan and R. Vemuri. An Efficient Battery-Aware Task Scheduling Methodology for Portable RC Platforms and Applications. In LNCS3203 Proceedings of the 14th International Conference on Field Programmable Logic and Applications, pages 669–678, Berlin Heidelberg, 2004. Springer-Verlag.
  118. J. Khan and R. Vemuri. An Iterative Algorithm for Battery-Aware Task Execution on Embedded Computing Platforms. In Design Automation and Test Europe, (DATE 2005), 2005.
  119. J. Khan and R. Vemuri, Energy Management in Battery-Powered Sensor Networks with Reconfigurable Computing Nodes, 15th International Conference on Field Programmable Logic and Applications (FPL), 2005.
  120. J. Khan and R. Vemuri. Battery-Efficient Task Execution on Reconfigurable Computing Platforms with Multiple Processing Units. In 12th Reconfigurable Architectures Workshop (RAW 2005), 2005.
  121. M. Ranjan and Amitava Bhaduri and Wim Verhaegen and Bhaskar Mukeherjee and Ranga Vemuri and Georges Gielen and Andrea Pacelli. Use of Symbolic Performance Models in Layout Inclusive RF Low Noise Amplifiers. In Proceedings of IEEE Ineternational Behavioral Modeling and Simulation Workshop, pages 130–134, October 2004.
  122. M. Ranjan, Wim Verhaegen, Amitava Bhaduri, Bhaskar Mukeherjee, Ranga Vemuri, Georges Gielen, Andrea Pacelli. Layout-in-Loop Synthesis of RF Low Noise Amplifiers using Efficient Parasitic-Inclusive Symbolic Performance Models. In Proceedings of International Workshop on Symbolic Analysis and Applications in Circuit Design, pages 59–62, September 2004.
  123. M. Mukherjee and R. Vemuri. A methodology for performance driven incremental placement with high level exploration. In The 2004 47th Midwest Symposium on Circuits and Systems, pages 1 441 – 1 444, 2004.
  124. M. Mukherjee and R. Vemuri. Simultaneous scheduling, binding and layer assignment for synthesis of vertically integrated 3d systems. In Proceedings of IEEE International Conference on Computer Design: VLSI in Computers and Processors, pages 222–227, 2004.
  125. M. Mukherjee and R. Vemuri. On physical-aware synthesis of vertically integrated 3d systems. In Proceedings Of the 18th International Conference on VLSI Design, 2005.
  126. B. Sethuraman, J. Khan and R. Vemuri. Battery-Efficient Task Execution on Portable Reconfigurable Computing Platforms. In IEEE International SOC Conference, pages 237–240, April 2004.
  127. G. Wolfe and R. Vemuri. Adaptive sampling and modeling of analog circuit performance parameters with pseudo-cubic splines. In IEEE/ACM International Conference on Computer Aided Design, Nov 2004.
  128. H. Yang, M. Ranjan, W. Verhaegen, M. Ding, R. Vemuri and G. Gielen. Symbolic sensitivity analysis using element-coefficient diagrams. In the proceeding of SAMCD 04, page 75, Sept. 2004.
  129. H. Yang, M. Ranjan, W. Verhaegen, M. Ding, R. Vemuri and G. Gielen. Efficient symbolic sensitivity analysis of analog circuits using element-coefficient diagrams. In Proceedings of ASP-DAC ’05, Jan. 2005.
  130. Raoul Badaoui, Hemanth Sampath, Anuradha Agarwal and Ranga Vemuri, A High Level Language for Pre-Layout Extraction in Parasite-Aware Analog Circuit Synthesis, Great Lakes Symposium on VLSI (GSVLSI), 2004.
  131. M. Ranjan and Wim Verhaegen and Hemath Sampath and Anuradha Agarwal and Ranga Vemuri and Georges Gielen. Fast, Layout-Incl. Analog Circuit Syn. using pre-compiled parasitic-aware symbolic performance models. In Proceeding of Design Automation and Testing in Europe Conference, pages 604–609, February 2004.
  132. A. Agarwal, H. Sampath, V. Yelamanchili and R. Vemuri, Accurate Estimation of Parasitic Capacitances in Analog Circuits, Proc. Of IEEE/ACM Design Automation and Test in Europe, Conference, February 2004.
  133. Manish Handa and Ranga Vemuri, A Fast Algorithm for Finding Maximal Empty Rectangles for Dynamic FPGA Placement, IEEE/ACM Design Automation and Test in Europe (DATE-04), Feb, 2004.
  134. A. Doboli, N. Dhanwada, A. Nunez-Aldana and R. Vemuri, A Library Based Approach to Synthesis of Analog Systems from VHDL-AMS Specifications, ACM Transactions on Design Automation of Electronic Systems (ACM-TODAES), vol. 9, no. 2, pp. 238-271, April 2004.
  135. Renqiu Huang and Ranga Vemuri, Forward-looking Macro Generation and Relational Placement During High Level Synthesis to FPGAs, Reconfigurable ArchitectureWorkshop (RAW-04), Santa Fe, NM, USA, Apr. 2004.
  136. Manish Handa and Ranga Vemuri, Hardware Assisted Two Dimensional Ultra Fast Placement, Reconfigurable Architecture Workshop (RAW-04), Santa Fe, NM, USA. Apr. 2004.
  137. G. Wolfe, M. Ding and R. Vemuri, Adaptive Sampling and Modeling of Analog Circuit Performance Parameters, Proceeding of the IFIP International Conference on Very Large Scale Integration (IFIP-VLSI), Darmstadt, Germany, pp. 142-147, Dec., 2003.
  138. H. Sampath and R. Vemuri, MSL: A High-Level Language for Parameterized Analog and Mixed-Signal Layout Generators, Proceeding of the IFIP International Conference on Very Large Scale Integration (IFIP-VLSI), Darmstadt, Germany, pp. 416-421, December 2003.
  139. A. Doboli and R. Vemuri, Behavioral Modeling for High Level Synthesis of Analog and Mixed-Signal Systems from VHDL-AMS, IEEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, vol. 22, no. 11., pp. 1504-1520, November 2003. (Among the top 10 most downloaded TCAD papers in 2005.)
  140. A. Doboli and R. Vemuri, Exploration Based High Level Synthesis of Linear Analog Systems Operating at Low/Medium Frequencies, IEEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, vol. 22, no. 11., pp. 1556-1568, November 2003.
  141. Madhubanti Mukherjee and Ranga Vemuri, A Novel Synthesis Strategy Driven by Partial Evaluation Based Circuit Reduction for Application Specific DSP Circuits, 21st International Conference on Computer Design (ICCD), pp. 436-440, San Jose, CA, Oct 2003.
  142. G. Wolfe, R. Vemuri, Extraction and use of neural network models in automated synthesis of operational amplifiers, IEEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, vol. 22, no. 2, pp. 198-212, February 2003.
  143. Manish Handa, Rajesh Radhakrishnan, Madhubanti Mukherjee and Ranga Vemuri, A Fast Macro Based Compilation Methodology for Partially Reconfigurable FPGA Designs, 16th International Conference on VLSI Design, January, 2003.
  144. J. Khan, M. Handa and R. Vemuri. iPACE-V1: A Portable Adaptive Computing Engine for Real Time Applications. In LNCS2438 Proceedings of the 12th International Conference on Field Programmable Logic and Applications, pages 69–78, Berlin Heidelberg, 2002. Springer-Verlag.
  145. Karam S. Chatha and Ranga Vemuri, Hardware-Software Partitioning and Pipelined Scheduling of Transformative Applications, IEEE Transactions on VLSI Systems, vol. 10. no. 3, pp. 193-208, June 2002.
  146. S. Siva, R. Vemuri, W. Vanfleet, J. Franco and J. Schlipf, Reconfigurable Interconnect Synthesis via Quantified Boolean Satisfiability, Fifth International Symposium on the Theory and Applications of Satisfiability Testing, May 2002.
  147. A. Doboli and R. Vemuri, A Functional Specification Notation for Co-Design of Mixed Analog-Digital Systems, Design, Automation and Test in Europe Conference (DATE), IEEE Press, March 2002.
  148. S. Dasasathyan, R. Radhakrishnan and R. Vemuri, Synthesis of Virtual Pipelines on Virtex-Based FPGAs, International Conference of VLSI Design and ASPDAC Joint Conference, IEEE Press, January 2002.
  149. R. Vemuri, M. Kaul, S. Katkoori and J. Roy, An Efficient Register Optimization Algorithm for High Level Synthesis from Hierarchical Behavioral Specifications, ACM Transactions on Design Automation of Electronic Systems (ACM-TODAES), vol. 7, no.1, pp. 189-216, January 2002.
  150. [Invited Chapter] Ranga Vemuri, Sreeram Govindarajan, Meenakshi Kaul, Vinoo Srinivasan, Iyad Ouaiss, Sujatha Sundararaman, Satish Ganesan and Awartika Pandey, Automated Design Synthesis and Partitioning for Adaptive Reconfigurable Hardware, in H. N. Teodorescu, L. Jain and D. Mlynek (eds.), “Hardware for Computational Intelligence,”, CRC Press, 2001.
  151. A. Doboli and R. Vemuri, A Regularity Based Hierarchical Symbolic Analysis Method for Large-Scale Analog Networks, IEEE Transactions on Circuits and Systems - II, vol. 48, no. 11, pp. 1054-1068, November 2001.
  152. N. Narasimhan, E.Teica, R. Radhakrishnan, S. Govindarajan and R. Vemuri, Theorem Proving Guided Development of Formal Assertions in a Resource-Constrained Scheduler for High-Level Synthesis, Formal Methods in Systems Design Journal (FMSD), Vol 19, Number 3, pp. 237-272, November 2001.
    • An earlier version of this paper [201] was presented at the International Conference on Computer Design (ICCD) 1998 and received the Best Paper Award at that conference.
  153. R. Radhakrishnan, E. Teica and R. Vemuri, Verification of Basic Block Schedules Using RTL Transformations, IFIP Correct Hardware Design and Verification Methods Workshop (CHARME), September 2001.
  154. E. Teica and R. Vemuri, Mechanizing in Higher-Order Logic Proofs of Correctness and Completeness for a Set of RTL Transformations, Theorem Proving in Higher Order Logics (TPHOL), September 2001. (Unreviewed progress paper.)
  155. Ranga Vemuri, Johan Sandstrom and Maya Rubeiz, Rapidly porting commercial electronic designs toradiation-hardened domain, AIAA Space 2001 Conference and Exposition, Albuquerque, August 2001.
  156. A. Kasat, I. Ouaiss and R. Vemuri, Memory Synthesis for FPGA Based Reconfigurable Computers, Proc. Intl. Workshop on Field-Programmable Logic and Applications (FPL’01), Springer, August 2001.
  157. A. Doboli and R. Vemuri, Fast Evaluation of Digital Switching Noise for Synthesis of Mixed-Signal Applications, Proc. International Workshop on Behavioral Modeling and Simulation (BMAS’01), Santa Rosa, 2001.
  158. A. Doboli and R. Vemuri, Hierarchical Optimization for Synthesis of Linear Analog Systems, Proc. International Symposium on Circuits and Systems (ISCAS), Sydney, 2001.
  159. S. Ganesan and R. Vemuri, Behavioral Partitioning in the Synthesis of Mixed Analog-Digital Systems, Proc. ACM/IEEE Design Automation Conference (DAC), pp. 133-138, June 2001.
  160. A. Doboli and R. Vemuri, Integrated High-Level Synthesis and Power-Net Routing for Digital Design Under Switching Noise Constraints, Proc. Design Automation Conference (DAC), June 2001.
  161. E. Teica and R. Vemuri, Mechanizing a Proof of Completeness for a Set of RTL Transformations, IFIP International Conference on VLSI and Systems on Chip (VLSI-SoC), 2001.
  162. Y. Pan, J. Li and Ranga Vemuri, Continuous Wavelet Transform On Reconfigurable Meshes, Proc. Workshop on Parallel and Distributed Computing in Image Processing, Video Processing, and Multimedia, April 23, 2001.
  163. Karam Chatha and R. Vemuri, MAGELLAN: Multiway Hardware-Software Partitioning and Scheduling for Latency Minimization of Hierarchical Control-Dataflow Task Graphs, Proc. 9th International Symposium on Hardware-Software Codesign (CODES 2001), Copenhagen, April 2001.
  164. I. Ouaiss and R. Vemuri, Global Memory Mapping for FPGA-Based Reconfigurable Systems, Proc. Reconfigurable Architectures Workshop (RAW’01), IEEE CS Press, April 2001.
  165. S. Ganesan and R. Vemuri, Analog-Digital Partitioning for Field-Programmable Mixed-Signal Systems, Proc. Advanced Research in VLSI (ARVLSI), March 2001.
  166. E. Teica, R. Radhakrishnan and R. Vemuri, On the Verification of Synthesized Designs Using Automatically Generated Transformational Witnesses, Proc. Design, Automation and Test in Europe (DATE’01), IEEE CS Press, March 2001.
  167. I. Ouaiss and R. Vemuri, Hierarchical Memory Mapping During Synthesis in FPGA-Based Reconfigurable Computers, Proc. Design, Automation and Test in Europe (DATE’01), pp. 650-657, IEEE CS Press, March 2001.
  168. Vinoo Srinivasan, Sriram Govindarajan and Ranga Vemuri, Fine-grained and Coarse-grained Behavioral Partitioning With Effective Utilization of Memory and Design Space Exploration for Multi-FPGA Architectures, IEEE Transactions on VLSI Systems, vol. 9, no. 1, pp. 140-158, February 2001.
  169. A. Doboli and R. Vemuri, A Regularity-Based Hierarchical Symbolic Analysis Method for Large Analog Networks, Proc. Design Automation and Test in Europe Conference (DATE), Munich, 2001.
  170. S. Ganesan and R. Vemuri, Library Binding for High-Level Synthesis of Analog Systems, Proc. International Conference on VLSI Design, IEEE Press, January 2001.
  171. Sujatha Sundararaman, Sriram Govindarajan and Ranga Vemuri, Application SpecificMacro Based Synthesis, Proc. International Conference on VLSI Design, IEEE Press, January 2001.
  172. M. Kaul and R. Vemuri, Design-Space Exploration for Block-Processing Based Temporal Partitioning of Runtime Reconfigurable Systems, in Jeffrey Arnold, Wayne Luk and Ken Pocek (eds.), “Field-Programmable Custom Computing Technology: Architecture, Tools, and Applications,” Kluwer Academic Publishers, 2000. (reprinted from 1577)
  173. R. Radhakrishnan, E. Teica and R. Vemuri, An Approach to High-Level Synthesis System Validation Using Formally Verified Transformations, International Conf. High Level Design Validation and Test Generation (HLDVT), IEEE Press, November 2000.
  174. Sriram Govindarajan and Ranga Vemuri, Tightly Integrated Design Space Exploration with Spatial and Temporal Partitioning in SPARCS, 10th International Conference on Field Programmable Logic, August 2000, Austria.
    • Best Paper Award Nomination, 10th International Conference on Field Programmable Logic and Applications, August 2000, Austria. From the about 50 papers from about 20 countries were selected for presentation at the conference, 3 were chosen as Best Paper candidates by the Best Paper Award committee.
  175. Karam Chatha and Ranga Vemuri, An Iterative Algorithm for Partitioning, Hardware Design-Space Exploration and Scheduling of Hardware-Software Systems, Design Automation for Embedded Systems Journal, vol. 5, no. 3/4, pp. 281-293, August 2000.
  176. Preetham Lakshmikantan, Vinoo Srinivasan, Sriram Govindarajan and Ranga Vemuri, Behavioral Partitioning with Synthesis for Multi-FPGA Architectures Under Interconnect, Area and Latency Constraints, Reconfigurable Architectures Workshop, 20 p., May 2000.
  177. Srinivas Katkoori and Ranga Vemuri, Scheduling for Low Power and Resource and Latency Constraints, International Symposium on Circuits and Systems, ISCAS 2000, May 2000.
  178. Alex Doboli, Nagu Dhanwada and Ranga Vemuri, A Heuristic Technique for System-Level Architecture Generation from Signal-Flow Graph Representations of Analog Systems, International Symposium on Circuits and Systems, ISCAS 2000, May 2000.
  179. Meenakshi Kaul and Ranga Vemuri, Design-Space Exploration for Block-Processing based Temporal Partitioning of Run-Time Reconfigurable Systems, The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology, vol. 24, pp. 181-209, April 2000.
  180. A. Doboli and R. Vemuri, Towards a Specification Notation for High-Level Synthesis of Mixed-Signal and Analog Systems, Proceedings of the International Workshop on Behavioral Modeling and Simulation (BMAS’00), Orlando, 2000.
  181. Satish Ganesan and Ranga Vemuri, An Integrated Temporal Partitioning and Partial Re-configuration Technique for Design Latency Improvement, Design Automation and Test in Europe Conference, (DATE’2000), pp. 320-325, March 2000.
  182. Sriram Govindarajan and Ranga Vemuri, Static List Time Constrained Scheduling Based on Topological Clustering, pp. 749, Design Automation and Test in Europe Conference, (DATE’2000), March 2000.
  183. Sree Ganesan and Ranga Vemuri, TechnologyMapping and Retargeting for Field-Programmable Analog Arrays, Design Automation and Test in Europe Conference, (DATE’2000), pp. 58-64, March 2000.
  184. Iyad Ouaiss and Ranga Vemuri, Efficient Resource Arbitration in Reconfigurable Computing Environments, Design Automation and Test in Europe Conference, (DATE’2000), pp. 560-566, March 2000.
  185. S. Govindarajan, V. Srinivasan, P. Laxmikantan and R. Vemuri, A Technique for Dynamic High Level Exploration During Behavioral Partitioning for Multi-Device Architectures, 13th International Conference on VLSI Design (VLSI’2000), IEEE Computer Society, pp. 212-219, Jan 2000.
    • Received the Best Paper Award at the conference. About 70 of the 180 submitted papers are accepted for presentation at the conference.
  186. Abhijit Ghosh and Ranga Vemuri, Formal Verification of Synthesized Mixed Signal Designs using *BMDs, 13th International Conference on VLSI Design (VLSI’2000), pp. 84-90, IEEE Computer Society, Jan 2000.
    • Received the Honoral Mention Award (Runner up for the Best Paper Award) at the conference. About 70 of the 180 submitted papers are accepted for presentation at the conference.
  187. Nazanin Mansouri and Ranga Vemuri, Automated Correctness Condition Generation for Formal Verification of Synthesized RTL Designs, Formal Methods in System Design Journal, Special issue on Formal Methods in Computer-Aided Design, (ed. Ganesh Gopalakrishnan and Phil Windley), vol. 16, pp. 59-91, January 2000.
  188. S. Ganesan and R. Vemuri, A Methodology for Rapid Prototyping of Analog Systems, International Conference on Computer Design (ICCD’99), IEEE Computer Society, October 1999.
  189. Abhijit Ghosh and Ranga Vemuri, Formal Verification of Synthesized Analog Designs, International Conference on Computer Design (ICCD’99), IEEE Computer Society, October 1999.
  190. A. Doboli, R. Vemuri, A Decomposition-based Symbolic Analysis Method for Analog Synthesis from Behavioral Specifications, in “VLSI: Systems on a Chip”, editors: L. M. Silveira, S. Devadas, R. Reis, Kluwer, 1999, pp. 305-317.
  191. Adrian Nunez-Aldana and Ranga Vemuri, A Linear Programming Approach for Synthesis of Mixed-Signal Interface Elements, IFIP International Conference on VLSI, Portugal, December 1999.
  192. S. Ganesan, A. Nunez, N. Dhanwada, A. Doboli and R. Vemuri, Rapid Prototyping of Mixed Signal Systems from VHDL-AMS, International Workshop on Behavioral Modeling and Simulation (BMAS), October 1999.
  193. Awartika Pandey and Ranga Vemuri, Combined Temporal Partitioning and Scheduling for Reconfigurable Architectures, in Proceedings of SPIE International Symposium on Voice, Video & Data Communications, Reconfigurable Technology: FPGAs for Computing and Applications, September 1999.
  194. S. Ganesan and R. Vemuri, An FPGA/FPAA-Based Rapid Prototyping Environment for Mixed Signal Systems Reconfigurable Technology: FPGAs for Computing and Applications, SPIE Intl. Symp. Voice, Video and Data Communications, vol. 3844, Sep 99.
  195. Karam S. Chatha and Ranga Vemuri, Hardware-Software Codesign for Dynamically Re-configurable Architectures, 9th International Workshop on Field Programmable Logic and Applications (FPL’99), pp. 175-184, Springer Verlag, September 1999.
    • Received the Best Paper Award at the Workshop. 65 Papers from 20 countries were presented at this 3-day international workshop.
  196. Satish Ganesan, Abhijit Ghosh and R. Vemuri, High-level Synthesis of Designs for Partially Reconfigurable FPGAs, Military and Aerospace Applications of Programmable Devices and Technologies International Conference Proceedings (MAPLD), Sep 99. (accepted)
  197. Nazanin Mansouri and Ranga Vemuri, Integrating Observation Equivalence Checking and Automated Theorem Proving for Verification of Designs at Register Transfer Level, Proceedings of FLoC’99 workshop on Run-Time Result Verification, July 1999.
  198. Adrian Nunez and Ranga Vemuri, Two Level Performance Estimator for High Level Synthesis of Analog Integrated Circuits with Feedback, Proc. 3rd IEEE International Conference on Design of Mixed Mode ICs and Applications, pp. 167-170, July 1999.
  199. Meenakshi Kaul, Ranga Vemuri, Sriram Govindarajan and Iyad Ouaiss, An Automated Temporal Partitioning and Loop Fission approach for FPGA based reconfigurable synthesis of DSP applications, IEEE/ACM Design Automation Conference (DAC’99), pp. 616-622, IEEE Computer Society Press, June 1999.
  200. A. Doboli, A. Nunez Aldana, N. Dhanwada, S. Ganesan and R. Vemuri, Behavioral Synthesis of Analog Systems using Two Layered Design Space Exploration, 36th Design Automation Conference (DAC’99), pp. 951-957, June 1999.
  201. Adrian Nunez-Aldana, Nagu Dhanwada, Alexa Doboli, Sree Ganesan and Ranga Vemuri, A Methodology for Behavioral Synthesis of Analog Systems, Proceedings of the IEEE Southwest Symposium on Mixed-Signal Design, pp. 162-167, Tucson, Arizona, April 1999.
  202. Meenakshi Kaul and Ranga Vemuri, Integrated Block-Processing and Design-Space Exploration in Temporal Partitioning for RTR Architectures, Reconfigurable Architectures Workshop (RAW’99), Springer-Verlag, pp. 606-615, April 1999.
  203. Vinoo Srinivasan, Shankar Radhakrishnan, Ranga Vemuri and Jeff Walrath, Interconnect Synthesis for Reconfigurable Multi-FPGA Architectures, Springer Verlag, 6th Reconfigurable Architectures Workshop, pp. 588-596, , Springer-Verlag, April 1999.
  204. Vinoo Srinivasan and Ranga Vemuri, Task Level Partitioning and RTL Design Space Exploration for Multi-FPGA Architectures, IEEE Symposium on FPGAs for Custom Computing Machines, FCCM99, 8 pages, April 99, Napa Valley, CA.
  205. Nagu R. Dhanwada, Adrian Nunez-Aldana and Ranga Vemuri, A Genetic Approach to Simultaneous Parameter Space Exploration and Constraint Transformation in Analog Synthesis, Proceedings of the International Symposium on Circuits and Systems (ISCAS), vol. 6, pp. 362-365, June 1999.
  206. Karam Chatha and Ranga Vemuri, An Iterative Algorithm for Partitioning and Scheduling of Area Constrained HW-SW Systems, Proc. 10th IEEE Workshop on Rapid Systems Prototyping (RSP’99), pp. 136-139, June 1999.
  207. Abhijit Ghosh, Sandeep Lodha and Ranga Vemuri, Hierarchical Scheduling in High Level Synthesis Using Resource Sharing Across Nested Loops, Proceedings of 9th Great Lakes Symposium on VLSI, pp. 140-143, IEEE Computer Society, March, 1999.
  208. Srinivas Katkoori and Ranga Vemuri, Accurate Resource Estimation Algorithms for Behavioral Synthesis, Proceedings of 9th Great Lakes Symposium on VLSI, pp. 338-339, IEEE Computer Society, March, 1999.
  209. Alex Doboli, Ranga Vemuri, A VHDL-AMS Compiler and Architecture Generator for Behavioral Synthesis of Analog Systems, Proceedings of Design, Automation and Test in Europe (DATE’99), IEEE CS Press, pp.338-345, March 1999.
    • One of the five papers nominated for the Best Paper Award at the conference. About 150 papers from over 30 countries were presented at this international conference. Conference has a 35% acceptance rate.
  210. Adrian-Nunez Aldana and Ranga Vemuri, An Analog Performance Estimator for Improving the Effectiveness of CMOS Analog Circuit Synthesis, Design, Automation and Test in Europe (DATE’99), IEEE CS Press, pp.406-411, March 1999.
  211. Meenakshi Kaul and Ranga Vemuri, Temporal Partitioning combined with Design Space Exploration for Latency Minimization of Run-Time Reconfigured Designs, Proceedings of Design, Automation and Test in Europe (DATE’99), IEEE CS Press, pp.202-209, March 1999.
  212. Nazanin Mansouri and Ranga Vemuri, Accounting for Various Register Allocation Schemes During Post-Synthesis Verification of RTL Designs, Proceedings of International Conference on Design, Automation and Test in Europe (DATE’99), pp. 223-230, IEEE Computer Society, Munich, Germany, March, 1999.
  213. Nagu R. Dhanwada, Adrian Nunez-Aldana and Ranga Vemuri, Hierarchical Constraint Transformation using Directed Interval Search for Analog System Synthesis, Proceedings of Design Automation and Test in Europe (DATE’99), IEEE Computer Society, pp. 328-335, Munich, Germany, IEEE Computer Society, March 1999.
  214. [Invited article] Ranga Vemuri, Cellular Logic, in John Webster (ed.), Encyclopedia of Electrical and Electronics Engineering, Addison-Wesley, Feb 1999.
  215. Nagu R. Dhanwada, Adrian-Nunez Aldana and Ranga Vemuri, Component Characterization and Constraint Transformation based on Directed Intervals for Analog Synthesis, 12th International Conference on VLSI Design (VLSI’99), IEEE Computer Society, pp. 589-596, Jan 1999.
  216. Vinoo Srinivasan and Ranga Vemuri, Throughput Optimization with Design Space Exploration during Partitioning for Multi-FPGA Architectures, ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays (FPGA’99), pp. 253, Feb 1999.
  217. Nagu R. Dhanwada, Adrian Nunez-Aldana and Ranga Vemuri, Automatic Constraint Transformation with Integrated Parameter Space Exploration in Analog System Synthesis, Asia and South Pacific Design Automation Conference (ASP-DAC’99), 4 pages, 1999, Jan 1999.
  218. Sree Ganesan and Ranga Vemuri, FAAR: A Router for Field-Programmable Analog Arrays, Proceedings of the 12th International Conference on VLSI Design (VLSI’99), India, IEEE Computer Society, pp. 556-563, January, 1999.
  219. K.S. Chatha and R. Vemuri, A Tool for Partitioning and Pipelined Scheduling of Hardware Software Systems, Proceedings of Eleventh IEEE International Symposium on System Synthesis (ISSS’99), IEEE Computer Society, pp. 145-151, Hsinchu, Taiwan, December 1998.
  220. Ranga Vemuri and Jeff Walrath, Abstract Models of Reconfigurable Architectures for Synthesis and Compilation, Configurable Computing: Technology and Applications, SPIE Symposium on Voice, Video and Data Communications, International Society for Optical Engineering, 12 pages, Boston, November 1998.
  221. Nazanin Mansouri and Ranga Vemuri, A Methodology for Automated Verification of Synthesized RTL Designs and Its Integration with a High-Level Synthesis Tool, 1998 International Conference on Formal Methods in Computer-Aided Design (FMCAD’99), 18 pages, Springer, November 1998.
  222. Meenakshi Kaul, Ranga Vemuri, Sriram Govindarajan and Iyad Ouaiss, An Automated Temporal Partitioning Tool for a class of DSP applications, Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT) Workshop on Reconfigurable Computing, pp. 22-27, October 1998.
  223. N. Narasimhan, E.Teica, R. Radhakrishnan, S. Govindarajan and R. Vemuri, Theorem Proving Guided Development of Formal Assertions in a Resource-Constrained Scheduler for High-Level Synthesis, International Conference on Computer Design (ICCD’98), pp. 392-399, IEEE Computer Society, October, 1998.
    • Received the Best Paper Award at the Conference. About 70 papers were presented at this conference, selected from among 190 submitted papers. This is one of the premier conferences in computer design and design automation.
  224. Viresh Paruthi, Nazanin Mansouri and Ranga Vemuri, Automatic Data Path Abstraction for Verification of Large Scale Designs, International Conference on Computer Design (ICCD’98), pp. 192-194, IEEE Computer Society, October, 1998.
  225. Alexa Doboli and Ranga Vemuri, The Definition of a VHDL-AMS Subset for Behavioral Synthesis of Analog Systems, 1998 IEEE/VIUF InternationalWorkshop on Behavioral Modeling and Simulation (BMAS’98), 7 pages, Oct 1998.
  226. A. Nunez-Aldana and Ranga Vemuri, A Hierarchical Modeling of Analog CMOS Components for Synthesis, Proceedings of the IEEE/VIUF International Workshops on Behavioral Modeling and Simulation (BMAS’98), pp. 26-28, Oct 1998.
  227. N. Narasimhan and R. Vemuri, On the Effectiveness of Theorem Proving Guided Discovery of Formal Assertions for a Register Allocator in a High-Level Synthesis, 11th Conference on Theorem Proving in Higher Order Logics (TPHOLs’98), pp. 367-386, September, 1998.
  228. Jeffrey Walrath and Ranga Vemuri, A Performance Analysis Environment for Adaptive Computing Systems, Proc. Conference on Military Applications of Programmable Logic Devices, 12 pages, Sep 1998.
  229. Meenakshi Kaul, Vinoo Srinivasan, Sriram Govindarajan, Iyad Ouaiss and Ranga Vemuri, Partitioning and Synthesis for Run-Time Reconfigurable Computers Using the SPARCS System, Proc. Conference on Military Applications of Programmable Logic Devices, 15 pages, Sep 1998.
  230. Praveen Chawla, Perry Alexander and Ranga Vemuri, A Search and Retrieval Tool to Enable System Design Through Intellectual Property Reuse, Proc. National Aerospace and Electronics Conference, pp. 620-626, July 1998.
  231. Ranga Vemuri, Adrian Nunez, Nagu Dhanwada, Alex Doboli, Paul Campisi, Sree Ganesan, Analog System Performance Estimation in the VASE, Proceedings of the Analog and Mixed-Signal Applications Conference, pp. 65-70, July, 1998.
  232. Adrian-Nunez Aldana, Alex Doboli and Ranga Vemuri, A Top-down Synthesis Methodology for Behavioral Mixed-Signal Systems Specified in VHDL-AMS, Proceedings of Second International Workshop on Design of Mixed-Mode Integrated Circuits and Applications, pp. 167-170, IEEE Press, July 1998.
  233. Iyad Ouaiss, Sriram Govindarajan, Vinoo Srinivasan, Meenakshi Kaul and Ranga Vemuri, A Unified Specification Model of Concurrency and Coordination for Synthesis from VHDL, Fourth International Conference on Information Systems, Analysis and Synthesis (ISAS98), Volume 3, pp. 771-778, International Institute of Informatics and Systematics, July 1998.
  234. Ranga Vemuri, Adrian Nunez, Nagu Dhanwada, Alexa Doboli, Sree Ganesan and Paul Campisi, VHDL Tools Eye Analog Synthesis, Electronic Engineering Times, pp. 94-118, July 13, 1998.
  235. K.S. Chatha and R. Vemuri, Performance Evaluation Tool for Rapid Prototyping of Hardware Software Codesigns, Proceedings of the Ninth IEEE Workshop on Rapid System Prototyping (RSP’98), IEEE Computer Society, pp. 218-224, Leuven, Belgium, June, 1988.
  236. S. Govindarajan, I. Ouaiss, M. Kaul, V.Srinivasan and R. Vemuri, An Effective Design System for Dynamically Reconfigurable Architectures, Proceedings of Sixth Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM’98), 2 pages, IEEE Computer Society, April 1998.
  237. Iyad Ouaiss, Sriram Govindarajan, Vinoo Srinivasan, Meenakshi Kaul and Ranga Vemuri, An Integrated Partitioning and Synthesis System for Dynamically Reconfigurable Multi-FPGA Architectures, Reconfigurable ArchitecturesWorkshop (RAW-98), pp. 31-36, Springer, March 1998.
  238. Jeffrey Walrath and Ranga Vemuri, A Performance Modeling and Analysis Environment for Reconfigurable Computers, Proc. Reconfigurable Architectures Workshop, RAW-98, pp. 19-24, Springer, March 1998.
  239. K.S. Chatha and R. Vemuri, RECOD: A Retiming Heuristic to Optimize Resource and Memory Utilization in HW/SW Codesigns, Proceedings of Sixth International Workshop on Hardware/Software Codesign, pp. 139-143, IEEE Computer Society, March, 1998.
  240. Meenakshi Kaul and Ranga Vemuri, Optimal Temporal Partitioning and Synthesis for Re-configurable Architectures, Proceedings of Design, Automation and Test in Europe (DATE), IEEE Computer Society, pp. 389-396, Feb 1998.
  241. V. Srinivasan, S. Radhakrishnan and R. Vemuri, Hardware/Software Partitioning with Integrated Hardware Design Space Exploration, Proc. of Design Automation and Test in Europe, IEEE Computer Society Press, pp. 28-35, February, 1998.
  242. Nagu R. Dhanwada and Ranga Vemuri, Constraint Allocation in Analog System Synthesis, Proceedings of the 11th International Conference on VLSI Design, pp. 253-258, IEEE Computer Society, Jan 1998.
  243. V. Srinivasan and R. Vemuri, Relaxation Based Retiming Heuristic for Resource-Constrained Loop Pipelining, Proc. 11th International conference on VLSI design, pp. 435-441, January, 1998.
  244. Srinivas Katkoori and Ranga Vemuri, Architectural Power Estimation Based on Behavioral Profiling, Journal of VLSI Design, Vol. 7, no. 3, pp. 255-270, 1998.
  245. [book] J. Hanna, R. Hillman, H. Hirsch, T. Noh and R. Vemuri (in alphabetic order), Using WAVES and VHDL for Effective Design and Testing, Kluwer Academic Publishers, 1997.
  246. Sriram Govindarajan and Ranga Vemuri, Dynamic Bounding of Successor Force Computations in the Force Directed List Scheduling Algorithm, Proceedings of IEEE International Conference on Computer Design (ICCD), pp. 752-757, IEEE Computer Society, Oct 1997.
  247. V. Natesan, Anurag Gupta, Srinivas Katkoori, Dinesh Bhatia and Ranga Vemuri, A Constructive Method for Data Path Area Estimation During High-Level VLSI Synthesis, Proceedings of ASP-DAC’97, 17 pages, 1997.
  248. Ranga Vemuri, Nagu Dhanwada, Adrian Nunez, Paul Campisi, VASE: VHDL-AMS Synthesis Environment - Tools for Mixed-Signal Systems, Proceedings of the Analog and Mixed-Signal Applications Conference, pp. 1C77-1C84, July, 1997.
  249. Jeffrey Walrath and Ranga Vemuri, Symbolic Evaluation of Performance Models for Tradeoff Visualization, Proceedings of the 34th ACM/IEEE Design Automation Conference, ACM Press, pp. 359-364, June, 1997.
  250. Sriram Govindarajan and Ranga Vemuri, Cone-Based Clustering Heuristic for List Scheduling Algorithms, Proceedings of European Design & Test Conference (ED&TC), pp. 456-462, IEEE Computer Society, March, 1997.
  251. Jeffrey Walrath and Ranga Vemuri, Performance Verification Using Partial Evaluation and Interval Analysis, Proceedings of European Design & Test Conference, p. 622, IEEE Computer Society Press, March, 1997.
  252. M. Vootukuru, Ranga Vemuri and Nand Kumar, Resource Constrained RTL Partitioning for Synthesis of Multi-FPGA Designs, Proceedings of the 10th International Conference on VLSI Design, IEEE Press, pp. 140-144, January 1997.
  253. P. A. Wilsey, R. Vemuri, P. J. Ashenden and N. Mause, Programmed Monitoring and Digital System Simulation, Current Issues in ElectronicModeling, vol. 8, pp. 33–53, December 1996.
  254. Ranga Vemuri, Naren Narasimhan, Ravi Kalyanaraman and Bill Bradley, Validation of Synthesized RTL Designs Using Simulation and Formal Verification International Conference on High Level Design Validation and Test Generation (HLDVT-96), November 1996.
  255. N. Narasimhan and R. Vemuri, Specification of Control Flow Properties for Verification of Synthesized VHDL Designs, Proceedings of the International Conference on Formal Methods in CAD, 19 pages, November, 1996.
  256. N. Kumar, V. Srinivasan and R. Vemuri, Hierarchical Behavioral Partitioning for Multi-Component Synthesis, Proc. European Design Automation Conference, pp. 212-219, IEEE Computer Society Press, September, 1996.
  257. Jeffrey Walrath and Karam S. Chatha and Ranga Vemuri, Performance Modeling and Trade-off Analysis During Rapid Prototyping, International Conference on Application-Specific Systems, Architectures, and Processors, pp. 313-322, IEEE Computer Society Press, August, 1996.
  258. N. Narasimhan, V. Srinivasan, M. Vootukuru et al., Rapid Prototyping of Codesigns for Reconfigurable Coprocessors, Proceedings of International Conference on ASAP, pp. 303-312, August, 1996.
  259. B. Benyo, A. Pataricza and R. Vemuri, High Fault Coverage Behavioral Test Generation, Proceedings of the IEEE European Test Workshop, 5 pages, June 1996.
  260. Ranga Vemuri, Ram Mandayam and Vijay Meduri, Performance Modeling Using PDL, IEEE Computer, vol. 29, no. 4, pp. 44-53, April 1996.
  261. Mike Doll and Ranga Vemuri, Automated WAVES Testset Compilation, pp. 181-190, VHDL Conference, VHDL International, Spring 1996.
  262. Madhavi Vootukuru, Ranga Vemuri and Nand Kumar, Partitioning of Register Level Designs for Multi-FPGA Synthesis, pp. 99-106, VHDL Conference, VHDL International, Spring 1996.
  263. Srinivas Katkoori and Ranga Vemuri, Simulation Based Architectural Power Estimation for PLA-Based Controllers, Proceedings of International Symposium on Low Power and Electronic Design, IEEE Press, pp.121-124, 1996.
  264. N. Narasimhan and R. Vemuri, Synchronous Controller Models for Synthesis from Communicating VHDL Processes, Ninth International Conference on VLSI Design, pp. 198-204, IEEE Press, January 1996.
  265. Srinivas Katkoori, Jay Roy and Ranga Vemuri, A Hierarchical Register Optimization Algorithm for Behavioral Synthesis, Proceedings of The 9th International Conference on VLSI Design, IEEE Press, pp. 126-134, January 1996.
  266. Srinivas Katkoori, Nand Kumar and Ranga Vemuri, High Level Profiling Based Low Power Synthesis Technique, Proceedings of International Conference on Computer Design 1995, IEEE Press, pp. 446-452, Oct 1995.
  267. Srinivas Katkoori and Ranga Vemuri, A Power Simulator for VHDL Structural Descriptions, Proceedings of VIUF Fall Conference 1995, Boston, October 15-18, pp. 4.17-4.25, 1995.
  268. W. Bradley and R. Vemuri, Performance Verification Using PDL and Constraint Satisfaction, Proc. IFIP International Conference on Computer Hardware Description Languages and Their Applications (CHDL’95), pp. 531-538, August 1995.
    • This paper also appeared as a Semiconductor Research Corporation Publication (Id. No. C94400) and is circulated to numerous SRC member companies and universities.
  269. Srinivas Katkoori, Nand Kumar, Leo Rader and Ranga Vemuri, A Profile Driven Approach for Low Power Synthesis, Proceedings of the IFIP VLSI Conference, August 29-June 1, pp. 759-765, 1995.
  270. Nand Kumar, Srinivas Katkoori, Leo Rader and Ranga Vemuri, Profile-Driven Behavioral Synthesis for Low Power VLSI Systems, IEEE Design & Test of Computers, vol. 12, no. 3, pp.70-84, Fall 1995.
  271. Ranga Vemuri and Ravi Kalyanaraman, Generation of Design Verification Tests for Behavioral VHDL Programs Using Path Enumeration and Constraint Programming, IEEE Transactions on VLSI Systems, vol. 3, no. 2, pp. 201-214, June 1995.
  272. Bill Bradley and Ranga Vemuri, Transformations for Functional Verification of Synthesized Designs, Proceedings of the 8th International Conference on VLSI Design, pp. 243-248, IEEE Computer Society Press, January 1995.
  273. Ram Vemuri and Ranga Vemuri, MCM Layer Assignment Using Genetic Search, Electronics Letters, vol. 30, no. 20, pp. 1635-1637, Sep 1994.
  274. Nand Kumar and Ranga Vemuri, An Efficient Parallel Algorithm for Finite State Machine Verification, Journal of Microelectronic Systems Integration, vol. 2, no. 2, pp. 3-14, 1994.
  275. Ram Vemuri and Ranga Vemuri, Genetic Algorithm for MCM Partitioning, Electronics Letters, vol. 30, no. 16, pp. 1270-1272, August 1994.
  276. Ranga Vemuri, Perry Alexander and Hal Carter, Board and MCM Level Synthesis for Embedded Systems: The COMET Cosynthesis Environment, Proceedings of the First Annual RASSP Conference, pp. 124-133, Washington DC, August 1994. (Published by the Advanced Research Projects Agency)
  277. Ramanand Mandayam and Ranga Vemuri, Performance Description Language, PDL, Extended Abstracts Volume of SRC Techcon’93, pp. 111-113, Atlanta, GA, September 1993. (Published by the Semiconductor Research Corporation)
  278. Bill Bradley, Ramanand Mandayam and Ranga Vemuri, Performance Verification using PDL and VHDL, Extended Abstracts Volume of SRC Techcon’93, p. 495, Atlanta, GA, September 1993. (Published by the Semiconductor Research Corporation)
  279. Ranga Vemuri, P. Mamtora, P. Sinha, Nand Kumar, Jay Roy and R. Vutukuru, Experiences in Functional Validation of a High Level Synthesis System, Proceedings of the 30th ACM/IEEE Design Automation Conference, pp. 194-201, IEEE Computer Society Press, IEEE Catalog Number 93CH3262-3, June 1993.
  280. Ramanand Mandayam and Ranga Vemuri, Performance Specification using Attribute Grammars, Proceedings of the 30th ACM/IEEE Design Automation Conference, pp. 661-667, IEEE Computer Society Press, IEEE Catalog Number 93CH3262-3, June 1993.
    • This paper also appeared as a Semiconductor Research Corporation Publication (Id. No. C93191) and is circulated to numerous SRC member companies and universities.
  281. Ramanand Mandayam and Ranga Vemuri, Performance Specification and Measurement, Proceedings of the IFIP Conference on Hardware Description Languages and Their Applications (CHDL ’93), OCRI Publications, ISBN 1-895634-02-4, pp. 267-284, Ottawa, April 1993.
    • This paper also appeared as a Semiconductor Research Corporation Publication (Id. No. C93117) and is circulated to numerous SRC member companies and universities.
  282. Ranga Vemuri, Nand Kumar, Ning Ren and Ram Vemuri, A Multicomponent Synthesis Environment for VHDL Specifications Proceedings of the VHDL Spring 1993 Conference, pp. 1-18, VHDL International, Ottawa, April 1993.
  283. Nand Kumar, Ram Vemuri and Ranga Vemuri, Partitioning for Multicomponent Synthesis from VHDL Specifications, Proceedings of the VHDL Spring 1993 Conference, pp. 19-28, VHDL International, Ottawa, April 1993.
  284. Ranga Vemuri, Nand Kumar, R. Vutukuru, P. Subba Rao, P. Sinha, Ning Ren, Paddy Mamtora, Ram Mandayam, Ram Vemuri and Jay Roy, An Integrated Multicomponent Synthesis Environment for Multichip Modules, IEEE Computer, vol. 20, no. 4, pp. 62-74, April 1993. (This paper also appeared as a Semiconductor Research Corporation Publication Id. No. C93192).
  285. Jeff Kehl and Ranga Vemuri, CAD for Radiation-Tolerant VLSI Design, Proceedings of the Fifth Annual Space System Health Management Technology Conference, UC-NASA Space Engineering Research Center, Cincinnati, Ohio, 1993.
  286. Jim Breisch, Jeff Kehl, Kevin McGonnegle, Mark Yarch and Ranga Vemuri, A VLSI Implementation of the RESID Fault Detection Algorithm for SSME Health Monitoring, Proceedings of the Fifth Annual Space System Health Management Technology Conference, UC-NASA Space Engineering Research Center, Cincinnati, Ohio, 1993.
  287. P. A. Wilsey, Ranga Vemuri and N. Mause, Instrumenting the Digital System Simulation Environment, Proc. of the 1993 Western Simulation Multiconference on Simulation in Engineering Education, Society for Computer Simulation, pp. 224-229, January 1993.
  288. Ranga Vemuri, Minor Program in VLSI Systems Engineering and the VLSI Design and Test Laboratory, Proceedings of the ASEE Annual Conference, American Society for Engineering Education, pp. 1-4, 1993.
  289. Ram Vemuri, Bob Hoffa and Ranga Vemuri, An Application of Genetic Algorithms to the Layer Assignment Problem in Multichip Modules, Proceedings of the IEEE International Conference on Systems, Man and Cybernetics, pp. 1520-1525, October, 1992.
  290. Nand Kumar and Ranga Vemuri, Finite State Machine Verification Using MIMD Machines, Proceedings of the European Design Automation Conference, pp. 514-520, IEEE Computer Society Press, IEEE Catalog Number 92CH3126-0, September 1992.
  291. Rajiv Dutta, Jay Roy and Ranga Vemuri, Distributed Design Space Exploration for High-Level Synthesis Systems, Proceedings of the 29th ACM/IEEE Design Automation Conference, IEEE Catalog Number 92CH3144-3, pp. 644-650, June 1992.
  292. Jay Roy, Nand Kumar, Rajiv Dutta and Ranga Vemuri, DSS: A Distributed High-Level Synthesis System, IEEE Design and Test of Computers, vol. 9, no. 2, pp. 18-32, June 1992.
    • An earlier version of this paper [273] was presented at the 1991 VHDL Conference and received the Best Paper Award at that conference.
  293. Raghu Vutukuru, P. Subba Rao and Ranga Vemuri, Boundary Scan Test Structures and Test-Bench Compilation in a Multichip Module Synthesis System, Proceedings of the IEEE Multichip Modules Conference, pp. 44-47, IEEE Computer Society Press, IEEE Catalog Number 92CH3124-5, March 1992.
  294. Ranga Vemuri and Anuradha Sridhar, Verification of Preconditions of Design Transformations, Proceedings of the IFIP International Workshop on Computer-Aided Verification, 15 pages, Aalborg, Denmark, July 1991.
  295. Jay Roy and Ranga Vemuri, DSS: A Distributed Synthesis System for VHDL Specifications, Proceedings of the VHDL Conference, pp. 39-46, VHDL International, April 1991.
    • Received the Best Paper Award at the Conference. About 60 papers were presented at this conference.
  296. H. Carter, Ranga Vemuri, P. Wilsey, J. Aylor, R. Waxman and T. Hartrum, High Speed Acceleration of VHDL Simulation, Synthesis and ATPG: Overview of the QUEST Project, Proceedings of the VHDL Spring 1991 Conference, pp. 85-90, VHDL International, April 1991.
  297. Ram Vemuri and Ranga Vemuri, Genetic Synthesis: Performance Driven Logic Synthesis Using Genetic Evolution, Proceedings of the IEEE Great Lakes Symposium on Very Large Scale Integrated (VLSI) Systems, pp. 312-317, IEEE Computer Society Press, IEEE Catalog Number 91TH0364-0, Kalamazoo, March 1991.
  298. Kapila Udawatta and Ranga Vemuri, On the Synthesis of VHDL’s Signal Assignments and Communicating Processes, Proceedings of the IFIP International Workshop on Electronic Design Automation Frameworks, Springer, 20 pages, Charlottesville, November 1990.
  299. Kapila Udawatta and Ranga Vemuri, VHDL Synthesis Based on a FSM Network Model, Proceedings of the VHDL Users Conference, Oakland, October 1990.
  300. Ranga Vemuri, Jay Roy, K. Udawatta and N. Kumar, Distributed Synthesis Systems Research, VHDL Methods Workshop, Chalottsville, Aug 1990.
  301. Ranga Vemuri, How to Prove the Completeness of Register Level Design Transformations, Proceedings of the 27th ACM/IEEE Design Automation Conference, pp. 207-212, IEEE Press (Catalog No. 90-24CH2094-4), June 1990.
  302. Anuradha Sridhar and Ranga Vemuri, Automatic Precondition Verification for High-Level Design Transformations, Proceedings of the IEEE International Conference on Circuits and Systems, pp. 2654-2657, IEEE Press (Catalog No. 90CH2868-8), May 1990.
  303. Ranga Vemuri, On the Notion of the Normal Form Register Level Structures and Its Applications in Design Space Exploration, Proceedings of the European Design Automation Conference, pp. 46-51, IEEE Computer Society Press (Order No. 2024), March 1990.
  304. Ranga Vemuri, A Formal Model for Register Transfer Level Structures and Its Applications in Verification and Synthesis, Proceedings of the IFIP International Workshop on Applied Formal Methods for Correct VLSI Design, pp. 77-96, Published by IMEC-IFIP, Belgium, November 1989.
  305. Ranga Vemuri, On the Effectiveness of a System of RT-Level Transformations for Design Space Exploration, Proceedings of the 32nd Midwest Symposium on Circuits and Systems, pp. 1078-1084, IEEE Press (Catalog No. 89CH2785-4), August 1989.
  306. Ranga Vemuri and C. A. Papachristou, On the Control-Step Assignment in a Transformational Synthesis System : C-Expressions and Their Algebra, Proceedings of the International Workshop on Logic and Architecture Synthesis for Silicon Compilers, 12 pages, France, May 1988.
  307. Ranga Vemuri and C. A. Papachristou, A Formalism and an Approach to Register Transfer Level Synthesis, Proceedings of the ACM/IEEE-CS Workshop on High-Level Synthesis, Orcas Island, USA, Jan 1988.
  308. M. C. Chandra Mouly, K. R. Devi, K. Sujata and R. Vemuri, Effect of Frequency of Operation on the Performance of Microwave Anechoic Chambers, SBMO International Microwave Symposium, Rio De Janeiro, July 1987.
  309. M. C. Chandra Mouly, N. V. Vani, K. R. Devi, K. Sujata and R. Vemuri, Design Considerations for Tapered Microwave Anechoic Chambers, Journal of IE(I), vol. 65, ET-3, pp. 60-64, February 1985.
  310. M. C. Chandra Mouly, Ranga Vemuri and C. Raja Rao, Microwave Anechoic Chambers: A Novel Design Approach, Conference on Precision Electromagnetic Measurements, 3C14, Netherlands, August 1984.
  311. M. C. Chandra Mouly and Ranga Vemuri, Effect of Source Antenna Directivity on the Performance of an Anechoic Chamber, Journal of IE(I), vol. 64, ET-3, pp. 60-62, February 1984.
  312. M. C. Chandra Mouly, Ranga Vemuri and C. Raja Rao, Towards Optimal Designs for Microwave Anechoic Chambers, The National Telesystems Conference, pp. 393-396, San-Francisco, November 1983.