The globalization of the IC manufacturing industry has increased the need for securing hardware IP from counterfeiting, overproduction and malicious modifications. DDEL is working in this area by investigating vulnerabilities in hardware design, specifically looking at hardware Trojans, split manufacturing, logic encryption, and reverse engineering.

A hardware Trojan is a malicious circuit inserted into the genuine design without the designer’s knowledge. Hardware Trojans are designed in such a way that they are triggered on a rare condition. A Trojan makes use of this property to avoid detection during normal post-fabrication testing. Furthermore, lack of knowledge of the architecture or impact of the hardware Trojan, makes detection more difficult. Distributed and networked embedded systems are becoming increasingly popular in numerous application areas ranging from home automation to infrastructure safety. Various IoT (Internet of Things) gadgets are being used to monitor and control appliances which are expected to operate in a safe manner. One particularly stealthy yet intrusive way of undermining the security of an embedded system is through the insertion of Hardware Trojans. Research at DDEL focuses on design as well as detection of hard-to-detect Hardware Trojans that are inserted into combinational circuits  as well as sequential circuits (with or without scan chains).

Split Manufacturing is the most efficient method to thwart any possible reverse engineering and overproduction in untrusted foundries. By splitting a circuit design into two parts, Front-End-Of-Line(FEOL) layers contains all transistors and most low level wire connections are fabricated at untrusted foundries while Back-End-Of-Line(BEOL) signals consists of signal connections fabricated in a secure foundry. By analyzing any physical design hints and logic function, the attackers in untrusted foundries are trying to recover the correct BEOL signal connections. Methods that can recover the BEOL signals correctly and efficiently are researched thus possible defense can be proposed to protect any possible reverse engineering in Split Manufacturing. Physical hints we have right now: combinational cycles, placement and routing results, fanin/fanout load capacitance, cell lib pattern matching, etc. Logic hints mainly focused on satisfiability checker (SAT) and binary decision diagram (BDD).

Logic encryption/obfuscation has emerged as a viable security measure against IC counterfeiting and IP piracy. Logic encryption locks the input-output functionality of a circuit using an additional set of inputs called key inputs. If an invalid value is applied to the key inputs, the circuit’s input-output relation is corrupted. Recently, Boolean satisfiability based attacks have proven to be effective against logic encryption techniques. In these attacks, a CNF formula is derived from the locked netlist and fed to a SAT solver in order to obtain the correct key value. These attacks prompted the research community to look for various types of SAT-resistant logic encryption techniques. Most such techniques try to delay the SAT-based attacks by making the runtime exponential. Removal attacks and bypass attacks are other types of attack methods that have proven to be effective against some of the SAT-resistant techniques. DDEL is working on designing intelligent logic encryption schemes to thwart various types of attacks as well as on developing new attack schemes to identify unexplored vulnerabilities in current encryption schemes.

The process of detecting and localizing errors in integrated circuits after fabrication is referred to as post-silicon validation and debug. Due to the increasing complexity of SoCs, the effort spent in Post-Silicon Validation continues to grow.  Limited observability and controllability are the major challenges in post-silicon validation as the prototypes have already been manufactured. Therefore trace buffer based run-time techniques have been proposed and applied to post-silicon validation for bug detection and localization. A small subset of internal signals across a predefined number of clock cycles are recorded in trace buffer during run-time. Consequently, the quality of observability depends on the number of internal signals whose values can be inferred through analyzing the run-time data transferred off-chip from the trace buffer. The forward propagation and backward justification (FB) methods are fast and commonly used for signal restoration while the satisfiability based restoration methods demonstrate significant improvement but with less efficiency. Various trace signal selection algorithms are proposed to maximize restoration. Quality of these algorithms is influenced by the quality of the state restoration algorithm they use. Recently there is emerging interest in using assertions to address the challenges in post-silicon validation as well. DDEL is working on assertion based techniques in combination with SAT-based signal restoration methods for better quality of trace signal selection and fault localization.

Robot navigation means the robot's ability to determine its own position in its frame of reference and then to plan a path towards some goal location while collecting the information about its environment. To navigate in its environment, path planning, self-localization and map building are very essential. Echolocation is one of the techniques used for navigation where the source emits a high frequency call and navigates through an environment by gathering the echoes emitted by various objects. The purpose of the project is to build a robot prototype that navigates through an indoor environment and collects the information for sonar based mapping applications. The designed robot uses omni wheels for easier control and maneuverability around the environment. A raspberry pi is used to gather and process the information from sensors like IMU, laser scanner and a camera. A custom designed sonar DAQ system is mounted on the robot to perform echolocation. The robot is controlled wirelessly by a laptop through Wi-Fi where the data gathered from the sensors is monitored. The data gathered can be further used for robot mapping and other sonar based application by implementing neural networks and machine learning.