PUBLICATIONS

 Papers Published in Refereed Journals

1.          S. R. Das, W. J. Hsu, Z. Chen and W. B. Jone, "Further studies on the matrix approach to the measurement and control problems of synchronous sequential machines - performance evaluation by computer simulation and application of specific heuristics," Computers and Electrical Engineering, Vol. 12, No. 3/4, pp. 161-173, 1986.

2.          S. R. Das and W. B. Jone, "Modified transition matrix and fault testing in sequential logic circuits under random stimuli with a specified measure of confidence," Cybernetics and Systems - An International Journal, 17:1-12, 1986.

3.          S. R. Das and W. B. Jone and K. W. Chiang, "A first order optimal algorithm for state identification in sequential logic using the concept of entropy," Cybernetics and Systems - An International Journal, 18:251-270, 1987.

4.          W. B. Jone, M. Pereira and C. A. Papachristou, "A new test scheduling method and its hardware support," IEEE VLSI Technical Bulletin, Vol. 3, pp. 85-103, Dec. 1988.

5.          S. R. Das, W. B. Jone, G. Fares and A. Nayak, "Probabilistic fault location in combinational logic network using concepts of fault distance and input feature," Cybernetics and Systems - An International Journal, 20:385-399, 1989.

6.          W. B. Jone and S. R. Das, "Multiple-output parity bit signature for exhaustive testing," Journal of Electronic Testing: Theory and Applications, Vol. 1, No. 2, pp. 175-178, June 1990.

7.          S. R. Das, W. B. Jone and K. L. Wong, "Probabilistic modeling and fault analysis in sequential logic using computer simulation," IEEE Transactions on Systems, Man and Cybernetics, Vol. 20, No. 2, pp. 490-498, March/April, 1990.

8.          W. B. Jone and S. R. Das, "A space compression method for built-in self-testing of VLSI circuits," International Journal of Computer Aided VLSI Design, Vol. 3, pp. 309-322, 1991.

9.          W. B. Jone and S. R. Das, "An improved analysis on random test length estimation," International Journal of Computer Aided VLSI Design, Vol. 3, pp. 393-406, 1991.

10.      W. B. Jone and A. Gleason, "Analysis of hamming count compaction scheme," Journal of Electronic Testing: Theory and Applications, Vol. 2, pp. 373-384, 1991.

11.      S. R. Das and W. B. Jone. "On random testing for combinational circuits with a high measure of confidence," IEEE Trans. on Systems, Man and Cybernetics, Vol. 22, pp. 748-754, July/August, 1992.

12.      W. B. Jone and P. H. Madden, "Multiple faults testing using single test sets for fan-out free circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 12, pp. 149-157, Jan. 1993.

13.      W. B. Jone, "Defect level estimation of circuit testing using sequential statistical analysis," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 12, pp. 336-348, Feb. 1993.

14.      W. B. Jone and C. J. Wu, "Multiple fault detection of parity checkers," IEEE Trans. on Computers, Vol. 43, pp. 1096-1099, Sep. 1994.

15.      S. R. Das, W. B. Jone, A. R. Nayak and I. Choi, "On testing of sequential machines using circuit decomposition and stochastic modeling," IEEE Trans. on Systems, Man and Cybernetics, Vol. 25, No. 3, pp. 489-504, March 1995.

16.      W. B. Jone and S. R. Das, "CACOP - a random pattern testability analyzer," IEEE Trans. on Systems, Man and Cybernetics, Vol. 25, No. 5, pp. 865-871, May 1995.

17.      W. B. Jone and C. A. Papachristou, "A coordinated circuit partitioning and test generation method for pseudo-exhaustive testing of VLSI circuits," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 14, No. 3, pp. 374-384, March 1995.

18.      C. L. Fang and W. B. Jone, "Timing optimization by gate resizing and critical path identification," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 14, No. 2, pp. 201-217, Februry, 1995.

19.      W. B. Jone, P. Gondalia and A. Gutjahr, "Realizing a high measure of confidence for defect level analysis of random testing," IEEE Trans. on VLSI Systems, Vol. 3, No. 3, pp. 446-450, Sep. 1995.

20.      W. B. Jone and D. Li, "On pseudorandom testability analysis using differential solutions," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 15, No. 7, pp. 815-825, July 1996.

21.      W. B. Jone, N. Shah, A. Gleason and S. R. Das, "PGEN - a novel approach to sequential circuit test generation," VLSI Design: An International Journal of Custom-Chip Design, Simulation and Testing, Vol. 4, pp. 149-166, 1996.

22.      W. B. Jone, Y. P. Ho, and S. R. Das, "Delay fault coverage enhancement using variable test observation times," Journal of Electronic Testing: Theory and Applications , Vol. 11, No. 2, pp. 131-146, Oct. 1997.

23.      W. B. Jone and K. S. Tsai, "Confidence analysis for defect level estimation of VLSI random testing," ACM Trans. on Design Automation of Electronic Systems, vol. 3, issue 3, pp. 389-407, 1998.

24.      S. R. Das, N. Goel, W. B. Jone, and S. R. Nayak, "Syndrome signature in output compaction for VLSI built-in self-test," VLSI Design: An International Journal of Custom-Chip Design, Simulation and Testing, vol. 7, no. 1, pp. 191-201, June 1998.

25.      J. Y. Chen, W. B. Jone, J. S. Wang, H. I. Lu, and T. F. Chen, "Segmented bus design for low-power systems," IEEE Trans. on VLSI systems, vol. 7, no. 1, pp. 25-29, March 1999.

26.      S. C. Chang, W. B. Jone, and S. S. Chang, "TAIR: testability analysis by implication reasoning," IEEE Trans. on Computer-Aided Design, vol. 19, no. 1, pp. 152-160, Jan. 2000.

27.      S. C. Chang, K. J. Lee, Z. Z. Wu, and W. B.Jone, "Reducing test application time by scan Flip-Flop sharing," IEE proceeding-Computes and Digital Techniques, vol. 147, pp. 42-48, Jan. 2000.

28.      J. C. Rau, W. B. Jone, S. C. Chang, and Y. L. Wu, "A tree-structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuits,"IEE proceeding-Computes and Digital Techniques, vol. 147-(5), pp. 343-348, Sep. 2000.

29.      C. H. Cheng, W. B. Jone, J. S. Wang, and S. C. Chang, "Low-speed scan testing of charge-sharing faults for CMOS domino circuits," IEE Electronic Letters, vol. 36, no. 20, 1684-1685, vol. 36, Sep. 2000.

30.      S. C. Chang, C. H. Cheng, W. B. Jone, S. D. Li, and J. S. Wang, "Charge sharing alleviation and detection for CMOS domino circuits, IEEE Trans. on Computer-Aided Design," vol. 20, no. 2, pp. 266-280, Feb. 2001.

31.      S. C. Chang, K. Y. Chen, C. H. Cheng, W. B. Jone, and S. R. Das, "Random pattern testability enhancement by circuit rewiring," VLSI Design: An International Journal of Custom-Chip Design, Simulation and Testing , vol. 12, no. 4, pp. 537-549, Dec. 2001.

32.      W. B. Jone, D. C. Huang, S. C. Chang, and S. R. Das, "A stochastic method for defect level analysis of pseudorandom testing, " VLSI Design: An International Journal of Custom-Chip Design, Simulation and Testing, vol. 12, no. 4, pp. 457-474, Dec. 2001.

33.      D. C. Huang, W. B. Jone, and S. R. Das, "A redundancy-tolerant built-in self test and diagnosis method for multiple embedded memory arrays," VLSI Design: An International Journal of Custom-Chip Design, Simulation and Testing (accepted for publication).

34.      W. B. Jone, W. S. Yeh, C. W. Yeh, and S. R. Das, "An adapted path selection method for delay testing of digital circuits," IEEE Trans. on Instrumentation and Measurement, vol. 50, no. 6, pp. 1109-1118, Oct. 2001.

35.      S. R. Das, C. V. Ramamoorthy, M. H. Assaf, E. M. Petriu, and W. B. Jone, "Fault tolerance in systems design in VLSI using data compression under constraints of failure probabilities," IEEE Trans. on Instrumentation and Measurement, vol. 50, no. 6, pp. 1725-1747, Dec. 2001.

36.      S. R. Das, M. H. Assaf, E. Petriu, W. B. Jone and K. Charkrabarty,"A novel approach to designing aliasing-free space comparators based on switching theory formulation," IEEE Trans. on Instrumentation and Measurement, vol. 51, no. 4, pp. -, Aug. 2002.

37.      D. C. Huang and W. B. Jone, "A parallel built-in self-diagnostic method for embedded memory arrays," IEEE Trans. on Computer-Aided Design, vol. 21, no. 4, pp. 449-465, April 2002.

38.      D. C. Huang and W. B. Jone, "A parallel transparent BIST method for embedded memory arrays by tolerating redundant operations," IEEE Trans. on Computer-Aided Design, vol. 21, no. 5, pp. 617-628, May 2002.

39.      W. B. Jone, J. S. Wang, H. I. Lu, I. P. Hsu, and J. Y. Chen, "Design theory and implementation for low-power segmented bus systems," ACM Trans. on Design Automation of Electronic Systems (accepted for publication).

40.      W. B. Jone, D. C. Huang, S. C. Wu, and K. J. Lee, "An efficient BIST method for distributed small buffers," IEEE Trans. on VLSI Systems (accepted for publication).

Refereed Conferences and Symposia

1.          S. R. Das, W. B. Jone et. al., "Fault location in combinational logic networks by multistage binary tree classifier," IEEE International Conference on Circuits  and Computers,  New York, U. S. A., Sep. 28 - Oct. 1, 1982 (Proceeding pp. 624-628).

2.          S. R. Das and W. B. Jone, "Digital signature analysis in circuit fault detection," Presented at the National Seminar on Microwave Integrated Circuits, Communications and Signal processing (MICCASP), Osmania University, Hyderabad, India,  Dec. 17-18, 1984 ( Conference Proceedings, pp. A79-A81 ) 緾 Invited contribution.

3.          S. R. Das, W. B. Jone and K. W. Chiang, "On an approach to finding the state identification sequences in sequential machines using the concept of entropy," Presented at the International Computer Symposium, Tamkang University, Taipei, Republic of China, Dec 12-14, 1984 ( Symposium Proceedings, Vol. 2, pp. 1141-1147 ).

4.          S. R. Das and W. B. Jone,  "Modified transition matrix and fault testing in sequential logic circuits under random stimuli with a specified measure of confidence," Presented at the International Conference on Computers, systems and Signal Processing, Bangalore, India, Dec 9-12, 1984 (Conference Proceedings, Vol. 2, pp. 707-711).

5.          S. R. Das, W. B. Jone and Z. Chen, "Realizing a high measure of confidence in random test generation for irredundant combinational logic networks," Presented at the International Computer Symposium, Taichung, Taiwan, Republic of China, Dec. 15-17, 1982 ( Symposium Proceedings, Vol. 2, pp. 905-914 ).

6.          S. R. Das, W. B. Jone and Z. Chen, "Digital signature analysis and fault testing in microprocessor-based systems," Presented at the Golden Jubilee Conference on advances in Information Science and Technology, Indian Statistical Institute, Calcutta, India, Jan. 11-14, 1982 ( Conference Abstracts, P. - ) - Invited contribution.

7.          S. R. Das, W. J. Hsu, Z. Chen and W. B. Jone, "Further studies on the matrix approach to the measurement and control problems of synchronous sequential machines - performance evaluation by computer simulation and application of specific heuristics," Presented at the International Computer Symposium, Taipei, Republic of China, Dec. 16-18, 1980 ( Symposium Proceedings, Vol. 2, pp. 1312-1324 ).

8.          S. R. Das, W. B. Jone, Z. Chen and S. Y. Lee, "Analysing the behavior of sequential logic circuits under random stimuli using the concept of modified transition matrix and fault testing with a specified degree of confidence", 16th Asilomar Conference on Circuits, Systems, and Computers, Pacific Grove, California,  U. S. A., Nov. 8-10, 1982 (accepted but not presented).

9.          S. R. Das, Z. Chen and W. B. Jone, "Random test generation for irredundant combinational logic networks with a high measure of confidence", Real-Time Systems Symposium, Miami Beach, Flo, U. S. A., Dec. 8-10, 1981 (accepted but not presented).

10.      C. A. Papachristou and W. B. Jone, "On test pattern selection of VLSI," IASTED International Conference on Reliability and Control, Paris, France, June 24-26, 1987. - Invited Contribution.

11.      S. R. Das, W. B. Jone and W. L. Wong, "Probabilistic modeling and fault analysis in sequential logic using computer simulation," IASTED International Conferences on Computer-aided Design and Applications, and Applied Simulation and Modeling, Vancouver, BC, Canada, June 1986 (Proceeding pp. 87-93).

12.      W. B. Jone, S. R. Das and C. A. Papachristou, "Derivation of minimum vertex cut and its application in VLSI testing," Accepted by 1988 International Computer Symposium.

13.      C. A. Papachristou and W. B. Jone, "Partitioning and pseudoexhaustive BIST of VLSI circuits," 1988 TECHCON, Sponsored by Semiconductor Research Corporation, (Proceeding pp. 160-163).

14.      W. B. Jone and C. A. Papachristou, "Is overlaying concurrent testing worthwhile ?,"The 11th Annual IEEE Workshop on Design for Testability, April 1988.

15.      W. B. Jone and C. A. Papachristou, "Methodology for parallel testing of VLSI circuits based on  partitioning and built-in self-testing  techniques," The 6th IEEE Built-In Self-Test Workshop, March 1988.

16.      W. B. Jone and C. A. Papachristou, "On partitioning for pseudo exhaustive testing of VLSI circuits," 21th IEEE International Symp. on Circuits and Systems, Espoo, Finland, June 7-9, 1988 (Proceedings, Vol. 2, PP. 1843-1846).

17.      W. B. Jone and S. R. Das, "Multiple-output parity bit signature generation for exhaustive testing," 1989 IASTED International Symp. On Reliability and Quality Control, June 1989.

18.      A.Gleason and W. B. Jone, "Hamming count - a compaction testing technique," IEEE International Conference on Computer Design, October 1989 (Proceeding pp. 344-347).

19.      W. B. Jone, C. A. Papachristou and M. Pereira, "A scheme for overlaying concurrent testing of VLSI circuits," 26th ACM/IEEE Design Automation Conference, June 1989 (Proceeding pp. 531-536).

20.      W. B. Jone and C. A. Papachristou, "A coordinated approach to partitioning and test pattern generation for pseudoexhaustive testing," 26th ACM/IEEE Design Automation Conference, June 1989 (Proceeding pp. 525-530).

21.      A. Gleason and  W. B. Jone, "Counter reduction techniques for hamming count," Fifth New Mexico Computer Science Conference, April 1990 (Proceeding pp. 36-63).

22.      W. B. Jone, "Defect level analysis of random and pseudorandom testing," 21th International Test Conference, October 1990 (poster section).

23.      W. B. Jone, "DSC - a space compression method," 23th IEEE International Symp. On Circuits and Systems, May 1990 (Proceeding pp. 2756-2759).

24.      A. Gleason and W. B. Jone, "Reduced hamming count and its aliasing probability," IEEE International Conference on Computer Design, October, 1991 (Proceeding pp. 356-359).

25.      A. Gleason and W. B. Jone, "Counter reduction techniques for hamming count," 24th IEEE International Symp. on Circuits and Systems, 1991 (Proceeding pp. 1980-1983).

26.      W. B. Jone, "Defect level estimation of random and pseudorandom testing," 22th International Test Conference, Nov. 1991, (Proceeding pp. 712-721).

27.      P. Gondalia, A. Gutjahr and W. B. Jone, "Realizing a high measure of confidence for defect level analysis of random testing," 24th International Test Conference, Oct. 1993 (Proceeding pp. 478-487).

28.      W. B. Jone and C. L. Fang, "Timing optimization by gate resizing and critical path identification," 30th ACM/IEEE Design Automation Conference, June 1993 (Proceeding pp. 135-140).

29.      W. J. Wu and W. B. Jone, "On multiple fault detection of parity checkers," 26th International Symposium on Circuits and Systems, May 1993 (Proceeding pp. 1515-1518).

30.      P. Gondalia, A. Gutjahr and W. B. Jone, "Realizing a high measure of confidence for defect level analysis of random testing," 4^th VLSI Design/CAD Workshop, August 1993 (Proceeding pp. 221-225).

31.      W. B. Jone and S. R. Das, "CACOP - a random pattern testability analyzer," 6th International Conference on VLSI Design, January 1993 (Proceeding pp. 61-64).

32.      S. R. Das, H. T. Ho and W. B. Jone, "Modified dynamic space compression for built-in self-testing of VLSI circuits, 37th Midwest Symp. on Circuits and Systems, August, 1994 (Proceeding 217-224).

33.      S. R. Das, W. B. Jone, A. R. Nayak and I. Choi, "On probabilistic testing of large-scale sequential circuits using circuit decomposition," 7th International Conference on VLSI Design, January 1994 (Proceeding 311-314).

34.      A. R. Nayak, W. B. Jone, and S. R. Das, "Designing general-purpose fault-tolerant distributed systems - a layered approach," 1994 International Conf. on Parallel and Distributed Systems, December 1994 (Proceeding 360-364).

35.      S. R. Das, H. T. Ho, W. B. Jone, and A. R. Nayak, "An improved output compaction technique for built-in self-test in VLSI circuits," 8th International Conference on VLSI Design, January 1995 (Proceeding 403-407).

36.      S. R. Das, N. Goel, and W. B. Jone, "Syndrome signature in output compaction for VLSI BIST," 9th International Conference on VLSI Design, January 1996 (Proceeding 337-338).

37.      J. C. Rau and W. B. Jone, "A tree-structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuits," The 7th VLSI Design/CAD Symposium, August 1996 (Proceeding 69-72).

38.      W. B. Jone, Y. P. Ho, and S. R. Das, "Delay fault coverage enhancement using multiple test observation times," The 10th International Conference on VLSI Design, January 1997 (Proceeding 106-110).

39.      S. R. Das, A. R. Nayak, M. H. Assaf, and W. B. Jone, "Realizing ultimate compression with acceptable fault coverage degradation to reduce MISR size in BIST applications by nonexhaustive test patterns," 1997 International Symp. on Circuit and Systems, June 1997 (Proceeding 2717-2720).

40.      C. W. Yeh, M. C. Chang, S. C. Chang, W. B. Jone and J. S. Wang, "Reducing power consumption by iterative gate sizing and voltage scaling," 8th VLSI Design/CAD Symposium, August 1997 (Proceeding 281-283).

41.      W. B. Jone and S. R. Das, "A stochastic method for defect level analysis of pseudorandom testing," 11th International Conference on VLSI Design, January 1998 (Proceeding 382-385).

42.      S. C. Chang, S. S. Chang, W. B. Jone, and C. C. Tsai, "A novel testability analysis by considering signal correlation," International Test Conference, October 1998 (Proceeding pp. 322-330).

43.      W. B. Jone, J. C. Rau, S. C. Chang, and Y. L. Wu, "A tree-structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuits," International Test Conference, October 1998 (Proceeding pp. 658-667).

44.      S. C. Chang, K. Y. Chen, W. B. Jone, and S. R. Das, "Random pattern testability enhancement by circuit rewiring," International Conference on VLSI Design, January 1999 (Proceeding pp. T9.4).

45.      W. B. Jone, D. C. Huang, S. C. Wu, and K. J. Lee, "An efficient BIST method for distributed small buffers," 17th IEEE VLSI Test Symposium, 1999 (Proceeding pp. 246-251).

46.      C. W. Yeh, M. C. Chang, S. C. Chang, and W. B. Jone, "Gate-level design exploiting dual supply voltages for power-driven applications," ACM/IEEE Design Automation Conference, 1999 (Proceeding pp. 68-71).

47.      C. H. Cheng, S. C. Chang, J. S. Wang, and W. B. Jone, "Charge sharing fault detection for CMOS domino logic circuits," International Symp. on Defect and Fault Tolerance in VLSI Systems, 1999 (Proceeding  pp. 77-85).

48.      W. B. Jone, W. S. Yeh, C. W. Yeh, and S. R. Das, "An adapted path selection method for delay testing of digital circuits," IEEE Instrumentation and Measurement Technology Conference, May 2000 (accepted).

49.      S. R. Das, J. Liang, E. M. Petriu, W. B. Jone, and K. Charkrabarty, "Data compression in space under generalized mergeability based on concepts of cover table and frequency ordering," IEEE Instrumentation and Measurement Technology Conference, May 2000 (accepted).

50.      C. H. Cheng, J. S. Wang, S. C. Chang, and W. B. Jone, "Charge sharing fault analysis and testing for CMOS domino circuits," First IEEE Latin-American Test Workshop, June 2000 (Proceeding pp. 59-64).

51.      C. H. Cheng, W. B. Jone, J. S. Wang, and S. C. Chang, "Low-speed scan testing of charge-sharing faults for CMOS domino circuits," International Symp. on Defect and Fault Tolerance in VLSI Systems, 2000 (Proceeding pp. 329-337).

52.      S. C. Chang, C. H. Cheng, W. B. Jone, S. D. Lee, and J. S. Wang, "Synthesis of CMOS domino circuits for charge sharing alleviation," International Conference on Computer-Aided Design, 2000 (Proceeding pp. 387-391).

53.      S. R. Das, M. Sudarma, J. Liang, E. Petriu, M. Assaf, and W. B. Jone, "Parity bit signature in response data compaction and built-in self-testing of VLSI circuits with compact test sets," 43^rd Midwest Symp. On Circuits and Systems, 2000 (accepted).

54.      D. C. Huang and W. B. Jone, "An efficient parallel transparent diagnostic BIST," Asian Test Symposium, 2000 (Proceeding pp. 299-303).

55.      C. H. Cheng, W. B Jone, S. C. Chang, and J. S. Wang, "Charge sharing fault analysis and testing for CMOS domino logic," Asian Test Symposium, 2000 (Proceeding pp. 435-440).

56.      D. C. Huang, W. B. Jone, and S. R. Das, "An efficient parallel transparent BIST method for multiple embedded memory buffers," International Conference on VLSI Design, 2001 (Proceeding pp. 379-384).

57.      D. C. Huang, W. B. Jone, and S. R. Das, "A parallel built-in self-diagnostic method for embedded memory buffers," International Conference on VLSI Design, 2001 (Proceeding pp. 397-402).

58.      S. R. Das, M. H. Assaf, E. M. Petriu, W. B. Jone, and K. Chakrabarty, "A novel approach to designing aliasing-free space compactors based on switching theory formulation using a new probability measure under generalized mergeability," IEEE Instrumentation and Measurement Technology Conference, May 2001 (Proceeding pp. 198-203).

59.      J. H. Jiang, W. B. Jone, and S. C. Chang, "Embedded core testing using broadcasting test architecture," International Symp. on Defect and Fault Tolerance in VLSI Systems, Oct. 2001 (Proceedings pp. 95-103).

60.      W. B. Jone, D. C. Huang, and S. R. Das, "An Efficient BIST Method for non-traditional faults of embedded memory arrays," IEEE Instrumentation and Measurement Technology Conference, May 2002 (Proceedings pp. 601-606).

61.      S. R. Das, M. H. Assaf, E. M. Petriu, and W. B. Jone, "Fault simulation and response compaction in full scan circuits using HOPE," IEEE Instrumentation and Measurement Technology Conference, May 2002 (Proceedings pp. 607-612).