WEN-BEN JONE

Curriculum Vitae

EDUCATION  

Case Western Reserve University (USA)

         PhD in Computer Engineering (August 1987)

         Thesis Title: Methodology for Parallel Testing of VLSI Circuits

         Based on Partitioning and Built-In Self-Testing Techniques

National Chiao-Tung University (Taiwan)

         ME in Computer Engineering (May 1981)

         Thesis Title: Random Testing and Logic Design

PROFESSIONAL ACTIVITIES AND SOCIETIES  

* Member of the IEEE

* Member of the IEEE Test Technology Technical Committee

* Member of the IEEE Technical Committee on Fault-Tolerant Computing

* Member of the Institute of Chinese Electrical Engineering

* Program committee of the 1993-1997 VLSI Desgn/CAD Symposium (in Taiwan)

* General Chair of the 1998 VLSI Design/CAD Symposium (in Taiwan)

* Program committee of the 1995-2001 Asia and South Pacific Design Automation Conference

* Program committee of the 1995-1996, 2000 Asian Test Symposium

* Publication Chair of the 2000 Asian Test Symposium

* Program committee of the 1998 International Conference on Chip Technology

* Program committee of the 2000 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems        

* Program committee of the 2001 Great Lake Symposium on VLSI         

* Referee of the International Journal of Modeling and Simulation

* Referee of the IEEE Computer Magazine (special issue on Software Tool for Hardware Test

* Referee of the IEEE International Test Conference

* Referee of the ACM/IEEE Design Automation Conference

* Referee of the International Journal of Computer Aided VLSI Design

* Referee of the Journal of Electronic Testing: Theory and Applications

* Referee of the IEEE Transactions on Computers

* Referee of the IEEE Transactions on Computer-Aided Design

* Referee of the IEEE Transactions on System, Man and Cybernetics

* Referee of the IEEE Transactions on VLSI Systems

* Referee of the IEEE Journal of Solid-State Circuits

* Referee of the IEEE Design & Test of Computers

* Referee of the National Science Foundation (USA)

* Referee of the National Science Council (Taiwan)

* Referee of the IEEE/ACM International Conference on Computer-Aided Design

* Referee of the International Conference on Parallel and Distributed Systems

* Referee of the Asian Test Conference

TUTORIALS

Parallel Test Pattern Generation for VLSI Circuits, 1994 International Conference on Parallel and Distributed Systems (jointly with Prof. Sunil R. Das)

WORK EXPERIENCE (ACADEMIC)

l        Assistant Professor

August 87 - May 92

Associate Professor (with tenure)

May 92 - February 93

Department of Computer Science

New Mexico Tech

Socorro, NM 87801

USA

l        Professor

February 93 - Jan. 2001

Department of Computer Science and Information Engineering

National Chung-Cheng University

Chiayi, Taiwan, ROC

l        Visiting Professor

1997 Summer

Department of Computer Science

Chinese University of Hong-Kong

Shatin, Hong-Kong

l        Associate Professor with tenure

Feb. 2001 - present

Department of Electrical & Computer Engineering and Computer Science

University of Cincinnati

Cincinnati, OH 45221

Sample Courses Taught

CS 121 Computer Programming

CS 122 Data Structure

CS 221 Introduction to System Programming

CS 240 Discrete Mathematics

CS 341 Switching Theory and Logic Design

CS 381 Computer Organization

CS 431 Computer Architecture (CAD Tools: Cadence Verilog-XL)

CS 460 Microprofessor Design

CS 550 Fault Tolerant Computing

CS 582 VLSI Testing (CAD Tools: Synopsys Test Compiler, Mentor Graphics Test Tools)

CS 531 Advanced Computer Architecture

CS 581 VLSI Systems Design (CAD Tools: Opus, Dracula, Design Compiler)

CS 590 Low Power Design for VLSI Systems

WORK EXPERIENCE (INDUSTRY)

l        R&D Officer and Systems Analyst

Military 206 Arsenal of Taiwan,  Republic of China

July 81 - May 83

l        Worked in the Digital System Lab., and designed highly reliable digital systems (used in missiles).

l        Assisted the Military Arsenal  Computer Center to develop the Arsenal Information Management Systems (in the networks of IBM S/34).

HONORS AND AWARDS

1.          Master Thesis was judged to be the Best Thesis and was awarded First Prize by the Chinese Electrical Engineering Asociation in 1981.

2.          Listed in the 15th Edition of Marquis Who's Who in the World, 1998, 2001

3.          Listed in the 6th Edition of Marquis Who's Who in Science and Engineering, 2002-2003.

4.          The First-Class Research Award, The National Science Council, Taiwan, Republic of China, 1994-1998

GRANTS

1.          VLSI Testing: from Research and Development and Division, New Mexico Tech, 1/1/89 - 1/1/90 (US$7000.00).

2.          Random Pattern Testability of VLSI Circuits: Supported by Sandia Nationa Laboratories, Contract Number Sandia 54-9306, 10/1/89 - 9/30/90 (US$30,000.00).

3.          Knowledge-Driven Test Generation for Sequential Circuits: Supported by Sandia National Laboratories, Contract Number Sandia 27-6108, 10/1/90 - 9/30/91 (US$30,000.00).

4.          Combinational Circuit Testing Using Random Testing Techniques: Supported by National Science Council, Taiwan, Republic of China, Contract Number NSC 83-0404-E-194-041, 2/1/93 - 1/31/94 (US$10,000.00).

5.          VLSI Systems Design: Equipment Funding, Supported by National Science Council, Taiwan, Republic of China, Contract Number NSC 83-0910-F-200-103, 9/1/93 - 1/31/94 (US$20,000.00).

6.          Pseudorandom Test Analysis using Differential Solutions: Supported by National Science Council, Taiwan, Republic of China, Contract Number NSC 84-0404-E-194-020, 2/1/94 - 7/31/95 (US$20,000.00).

7.          Defect Level Analysis, Yield Prediction, and Test Management for VLSI Fabrication and Testing: Supported by National Science Council, Taiwan, Republic of China, Contract Number NSC 85-2215-E-194-003, 8/1/95 - 7/31/96 (US$10,000.00).

8.          Delay Fault Coverage Enhancement Using Multiple Test Observation Times: Supported by National Science Council, Taiwan, Republic of China, Contract Number NSC 86-2215-E-194-004, 8/1/96 - 7/31/97 (US$ 13,000.00).

9.          Instruction Circuit Optimization for Low-Power Application-Specific Embedded Microcontroller: Supported by National Science Council, Taiwan, Republic of China, Contract Number NSC 86-2215-E-194-008, 8/1/96 - 7/31/97 (US$ 11,000.00).

10.      CPU Testing and Testability Features: Supported by National Science Council, Taiwan, Republic of China, Contract Number NSC 86-2622-E-008-010, 6/1/96 - 5/31/97, Jointly with Prof. K. J. Lee (US$ 63,000.00).

11.      An Adaptive Path Selection Method for Delay Testing: Supported by National Science Council, Republic of China, Contract Number 87-2215-E-194-007, 8/1/97-7/31/98 (US$ 14,000.00).

12.      Instruction Circuit Optimization for Low-Power Application-Specific Embedded Microcontroller: Supported by National Science Council, Taiwan, Republic of China, Contract Number NSC 87-2215-E-194-003, 8/1/97 - 7/31/98 (US$ 10,000.00).

13.      CPU Testing and Testability Features: Supported by National Science Council, Taiwan, Republic of China, Contrcat Number NSC 87-2622-E-008-010, 6/1/97 - 5/31/98, Jointly with Prof. K. J. Lee (US$ 45,000.00).

14.      Register Transfer Level Optimization for Low-Power Application-Specific Embedded Microcontroller: Supported by National Science Council, Taiwan, Republic of China, Contract Number NSC 88-2215-E-194-003, 8/1/98 - 7/31/99 (US$ 15,000.00).

15.      CPU Testing and Testability Features: Supported by National Science Council, Taiwan, Republic of China, Contrcat Number NSC 88-2622-E-008-010, 6/1/98 - 5/31/99, Jointly with Prof. K. J. Lee (US$ 45,000.00).

16.      Signal Integrity Testing for High-Performance VLSI Circuits in Deep Sub-Micron Technology: Supported by Ohio Board of Regent Computing Research Award, May 2001 -, (US$ 25,000.00).

Patents

1.          Built-in Self Test for Multiple Memories in a Chip, by K. J. Lee, J. Y. Wu, and W. B. Jone, US patent no. 09/268,666, ROC patent no. 123,572, Period: 2000/11/11-2018/6/22.

THESIS SUPERVISION

1.          Robert T. Perez (MS), Random Pattern Testability of FET Stuck-Open Faults in COMS Combinational Logic Circuits, Sep. 1988.

2.          Marcos Pereira (MS), Parallel Testing of VLSI Circuits, Feb. 1989.

3.          Patrick Madden (MS), Multiple Fault Detection of Fanout-free Circuits by Using Single Test Sets, Dec. 1989.

4.          Chi-Perng Yang (MS), PLA Testing by Adding Extra Inputs and Outputs, Sep. 1990.

5.          Cheng-Juei Wu (MS), On Multiple Fault Detection of Parity Checkers, Sep. 1990.

6.          Anita Gleason (PhD), Hamming-Count - A New Test Compression Method, Dec. 1990.

7.          Nigam Shah (MS), PGEN: A Novel Approach to Sequential Circuit Testing, Feb. 1991.

8.          Paresh Gondalia (MS), Defect Level and Yield Estimation for VLSI Fabrication, Dec. 1992.

9.          Jen-Liang Fang (MS), Critical path identification and timing optimization for circuit synthesis, August 1992.

10.      Dan Li (MS), On Pseudorandom Testability Analysis for VLSI Built-In Self-Testing, Dec. 1992.

11.      Kuen-Sien Tsai (MS), Confidence Analysis for Defect Level Estimation of VLSI Random Testing, June 1995.

12.      Yun-Pen Ho (MS), Delay Fault Coverage Enhancement Using Multiple Test Observation Times, June 1995.

13.      Jen-Chi Rau (MS), A Tree-Structured LFSR Synthesis Scheme for Pseodo-Exhaustive Testing of VLSI Circuits, June 1995.

14.      Hui-Nan Chang (MS), Low Power Design of VLSI Circuits Using Gate Resizing and Supply Voltage Scaling Techniques, June 1996.

15.      Wu-Sung Yeh (MS), An Adaptive Path Selection Method for Delay Testing, June 1996.

16.      Jen-Yu Chen (MS), Segmented Bus Design for Low-Power Systems, June 1997.

17.      Shuen-Chen Wu (MS), An Efficient BIST Method for Distributed Small Buffers, June 1997.

18.      I. Ping Hsu (MS), Implementation Techniques of Segmented Bus Design for Low-Power VLSI Chips, June 1998.

19.      Kwen-Yo Chen (MS), Random Pattern Testability Enhancement by Circuit Rewiring, June 1998.

20.      Tsong-Siu Wu (MS), Functional Testing for Superscalar Processors, June 1998.

21.      Chia-Haw Chang (MS), Testable Design and Implementation for a Microcontroller, June 1999.

22.      Wen-Chi Fong (MS), Low-Swing Bus Segmentation Design for Low-Power Systems, June 1999.

23.      Jia-Hui Jiang (MS), Embedded Core Testing Using Broadcast Test Architecture, June 2000.

24.      Sen-Tien Lin (MS), True Single Phase Circuit Design for Testability, June 2000.

25.      Jian-Chi Rau (PhD), Pseudo-Exhaustive Testing for VLSI Circuits Using Tree-Structured Test Scheme, Oct. 2000.

26.      Chin-Hua Chen (PhD), Charge-Sharing Alleviation and Detection for Domino Circuits, Nov. 2000.

27.      Der-Chen Huang (PhD), Built-In Self Testing and Diagnosis for Embedded Memory Arrays, Nov. 2000.

UNIVERSITY SERVICE

Academic Standards and Admissions Committee (1990-1991, NMT)

Chairman of the Academic Standards and Admissions Committee (1991-1992, NMT)

Council of University (1993-1998, NCCU)

DEPARTMENT SERVICE

Graduate Program Coordinator (1988-1989, NMT)

Faculty Search Committee (1988-1990, NMT)

Graduate Curriculum and Exams Committee (1988-1991, NMT)

Graduate Recruiting Committee (1993-1998, NCCU)

Departmental Equipment and Finance Committee (1993-1998, NCCU)

Council of College of Engineeting (CS&IE Representative, 1993-1998, NCCU)

Faculty Searching Committee (1993-1998, NCCU)