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CHEST 2021 Research Project Abstracts

P21_21: SHERLOCK: Power Side Channel Attack-Resilient Hardware using Emerging Reconfigurable Devices and Logic Locking
Topic Areas: New Approaches to Secure On-Shore Microelectronics Design and Manufacturing
Principal investigator: Dr. Houman Homayoun, University of California Davis
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The current state-of-the-art ASIC industry heavily relies on the globalized fabrication processes and hardware supply chain model [1]. While this movement has continued to benefit both participants and their global economy, the security of the underlying hardware is compromised due to various emerging hardware security threats such as overproduction, trojan insertion, reverse engineering, IP theft, and counterfeiting [2-4]. Many of the existing security works have targeted towards resolving a single vulnerability such as SAT-attack [5] or removal attack [6] while neglecting a potential threat of side-channel attacks. This motivates us to propose a novel approach for securing the hardware IPs during the fabrication process and supply chain via hardware obfuscation utilizing emerging spin-based devices.

In the first thrust, we aim to demonstrate the existing vulnerability in the current obfuscation techniques by innovative use of supervised and unsupervised deep learning. This effort will have the ability to accurately estimate the logic key by sampling the power traces even in the presence of process variation, signal noise, and perturbation caused by other non-deterministic components, without a need for reference hardware. This project’s second thrust aims to develop an effective mitigation solution to defend the hardware against many attacks, including SAT-attack [5], removal attack [6], and power side-channel attacks designed in thrust 1. The proposed primitive will resemble a defense-in-depth approach by thwarting the attacks using the reconfigurable obfuscation built using the emerging spin-based devices [7-12], which will have a symmetrical power consumption footprint reinforced with an extra layer of logic obfuscation. The runtime morphing offered by the emerging devices further helps curb many hardware security threats, while the symmetrical design of the emerging device shall eliminate the ability to infer the logic key using the power traces and various ML learning techniques developed in thrust one. This proposed obfuscation will potentially be leveraged and deployed using the off-the-shelf EDA tools with minimal overheads.