WELCOME TO VLSI TESTING COURSE
	Slides for VLSI Test

• Class 0
• Introduction
• Fault Modeling
• Extra Slices for Fault Modleing
• Fault Simulation
• Test Generation
• Extra Slices for Test Generation
• FAN Algorithms and a sample assigment
• Design for Testability
• Boundary Scan
• Built-in-Self-Test
• Memory Testing
• Extra Slides for Boundary Scan, BIST, Memory Test
• IDDQ Testing
• CPU Testing
• System-on-a-Chip Testing
• Automatic Test Equipment
• Analog Testing
• slides-fan.ppt  
• Memory Testing New!W)
• Delay Testing
• Syllabus
• Assignment 1: due on 4/23/08
• Assignment 1: Solution
• Assignment 2: due on 4/30/08
• Sample Midterm Test is here
• Solution to Assignment 2 is here
• Midterm Test Solution
• TA's E-mail: Divya Ramakrishnan, ramakrda@email.uc.edu
• Lab 1 Description is here
• Lab Management Note is here
• HP Logic Analyzer is here
• Lab 2 Description is here
• Guidelines to Prepare your PDF Slides

• 2006 Final Test Is Here
• Solution of 2006 Final Test Is Here
• 2007 Final Test Is Here

• Intel Testing Paper
• IBM Testing Paper
• SUN Testing Paper
• AMD Testing Paper
• ARM Testing Paper

• Introduction to VLSI Testing
• Automatic Test Pattern Generationb
• Fault Simulation
• Design for Testability